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Power integrity design in PCB circuit
2020-09-11 17:09:39
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In circuit design, we are generally concerned about the quality of the signal, but sometimes we are limited to the signal line, and treat the power supply and ground as ideal conditions. Although this can simplify the problem, in high-speed design, this simplification is no longer feasible. Although the direct result of circuit design is from the signal integrity, we can not ignore the power supply integrity design. Because the power integrity directly affects the signal integrity of the final PCB. Power integrity and signal integrity are closely related, and in many cases, the main cause of signal distortion is the power system. For example, the ground bounce noise is too large, the design of decoupling capacitor is not suitable, the loop influence is very serious, the division of multi power / ground plane is not good, the stratum design is unreasonable, and the current is not uniform.


1) Power distribution system

Power integrity design is a very complex thing, but how to control the impedance between the power system (power supply and ground plane) is the key to the design. In theory, the lower the impedance between power systems, the better. The lower the impedance, the smaller the noise amplitude and the smaller the voltage loss. In practical design, we can determine the target impedance we want to achieve by specifying the maximum voltage and power supply variation range, and then, by adjusting the relevant factors in the circuit, we can make the impedance of each part of the power supply system (related to frequency) to approximate the target impedance.


2) To rebound

When the edge rate of the high-speed device is less than 0.5 ns, the data exchange rate from the large capacity data bus is particularly fast. When it generates strong ripple in the power layer that can affect the signal, the power supply instability will occur. When the current through the ground loop changes, a voltage will be generated due to the loop inductance. When the rising edge is shortened, the current change rate increases and the ground rebound voltage increases. At this time, the ground plane (ground wire) is not the ideal zero level, and the power supply is not the ideal DC potential. When the gate circuit of simultaneous switch increases, the rebound becomes more serious. For 128 bit buses, there may be 50_ 100 I / O lines switch on the same clock edge. At this time, the inductances of the power and ground loops fed back to the I / O driver switching at the same time must be as low as possible, otherwise, there will be a voltage brush at the static state connected to the same ground. Rebound can be seen everywhere, such as chip, package, connector or circuit board, which may cause power integrity problems.

From the perspective of technology development, the rising edge of the device will only decrease, and the width of the bus will only increase. The only way to keep the ground bounce acceptable is to reduce the power and ground distribution inductance. For a chip, it means moving to an array chip, placing as much power and ground as possible, and the wiring to the package as short as possible to reduce inductance. For, package, it means moving layer package to make the ground plane spacing of power supply closer, as used in BGA package. For connectors, it means using more ground pins or redesigning the connector to have an internal power and ground plane, such as a connector based Ribbon cord. For a circuit board, it means making the adjacent power supply and ground plane as close as possible. Since the inductance is proportional to the length, the ground noise will be reduced by making the connection between the power supply and the ground as short as possible.


3) Decoupling capacitor

We all know that adding some capacitors between the power supply and the ground can reduce the noise of the system, but how many capacitors should be added to the circuit board? What is the appropriate capacitance value of each capacitor? Where is the best position for each capacitor? We have not seriously considered these problems, but only rely on the experience of designers. Sometimes we even think that the less the capacitance, the better. In the high-speed design, we must consider the parasitic parameters of the capacitor, and quantitatively calculate the number of decoupling capacitors, the capacitance value of each capacitor and the specific location of placement, so as to ensure that the impedance of the system is within the control range. A basic principle is that the required decoupling capacitance should not be less, and the redundant capacitance should not be less.


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