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IC Substrate Capabilities

IC Substrate Capabilities

IC Substrate Capabilities

IC Substrate Capabilities

IC Substrate Technical Capability
No.ItemDescriptionData &   Model 
1Sheng YiCore BrandSI643HU、SI10U、SI09U、SI07U、SI05U
   
2Mitsubishi Gas   ChemicalCore BrandHL832NXA、HL832NS、HL832NSR(LC)
3DooSanCore BrandDS-7409HGB(S)、DS-7409HGB(LE)、DS-7409HGB(X)
4PanasonicCore BrandR1515E/R1515H、
5Layer
1-8layer
6Min pattern size um25
7Min pattern   Space um25
8Min Pad  um80
9Min BGA Center   Space  um250
102L Min Thickness um80
112L Min   thickness/core/PP Thicknessum80/30
124L Min   thickness/core/PP Thicknessum150/30/20
136L Min   thickness/core/PP Thicknessum210/30/20
148L Min   thickness/core/PP Thicknessum300/30/20
15Soldermask Color
Green, Black
16SM Ink
EG23A、AUS308、AUS320、AUS410
14Surface treatment
Soft Gold   Plating,Hard Gold Plating,ENIG,OSP
18Flatnessum5max
19Min hole sizeum100
20Min Laser hole sizeum50
21Min thickness   tolerance um30
22Min PPum25
23Min Coreum40
24Minimum Finger Center   Distanceum65
25Min para-position   accuracyum15
26Support Process
Subtraction   process,  mSAP Process
27Soldermask toleranceum5

For more information about IC Substrate board, please click: IC Substrate Board


System-in-Package Substrate (SiP)

System-in-package is a system platform that assembles multiple heterogeneous wafers, sensing components, passive components, etc., into one package. Its applications include "multi-chip module (MCM)", "multi-chip package (MCP)", "stacked chip package", "package in package (PiP)", and "embedded component carrier board". System-in-package provides IC system designers with another computing function integration solution besides "System-on-Chip (SoC)". It has the advantages of integrating heterogeneous chips from different sources, being smaller and thinner, and entering the market quickly.

SIP can be a multi-chip module (Multi-chip Module; MCM) planar 2D package, and can also reuse the 3D package structure to effectively reduce the package area; and its internal bonding technology can be pure wire bonding (Wire Bonding), FlipChip can also be used, but the two can also be mixed. In addition to 2D and 3D packaging structures, another way of integrating components with multi-functional substrates can also be included in the scope of SIP. This technology mainly embeds different components in a multifunctional substrate, and can also be regarded as the concept of SIP to achieve the purpose of functional integration. Different chip arrangements and different internal bonding technologies enable SIP package types to produce diversified combinations. iPCB can be customized or flexibly produced according to the needs of customers or products.


Plastic Ball Gate Array Package Substrate (PBGA)

This is the most basic ball gate array substrate used in wire bonding and packaging. Its basic material is a copper foil substrate impregnated with glass fiber. The plastic ball gate array packaging substrate can be applied to chip packaging with a relatively high pin count. When the chip function is upgraded, the traditional lead frame package structure becomes inadequate with the increase in the number of output/input pins, and the plastic ball gate array package substrate provides a cost-effective solution.


Flip Chip Chip Scale Package Substrate (FCCSP)

The semiconductor chip is not connected to the substrate by wire bonding, but is interconnected with the substrate by bumps in a flip-chip state, so it is called "FCCSP" (Flip Chip Chip Scale Package). Flip-chip wafer-level size packaging will further show the cost advantage. In the recent past, the process cost of bumps on wafers has also continued to drop, which has also led to a faster reduction in packaging costs. Flip-chip chip-level size packaging has become a high-pin-count IC.


Flip Chip Ball Gate Array Package Substrate (FCBGA)

FC-BGA (Flip Chip-Ball Grid Array) substrate is a high-density semiconductor package substrate that can realize the high-speed and multi-functionalization of LSI chips. The flip chip ball gate array package has very excellent performance and cost advantages in the package of very high output/input pin count, such as a chip such as a microprocessor or an image processor.