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IC Substrate

IC Substrate

IC Substrate

IC Substrate

IC packaging substrate manufacturer
2021-07-20
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Author:kim

1.BGA ball grid array

BGA ball grid array.png

Also known as CPAC(Globe Top Pad Array Carrier).  Spherical contact display, one of the surface mount type package.  Spherical convex points are made on the back of the IC PCB in the form of display to replace the pins. LSI chips are assembled on the front of the PCB, and then the model is pressed into natural resin or sealed tightly by means of pouring.  Also known as the raised dot display carrier (PAC).  With more than 200 pins, it is a package for the multi-pin LSI.  The package body can also be made smaller than the QFP(four-pin flat package).  For example, the BGA of a 360 pin with a 1.5mm core distance is only 31mm square;  The QFP of 304 pin with a pin core distance of 0.5mm is 40mm square.  And the BGA does not have to worry about QFP - like pin variant issues.  

The package, developed by Motorola, an American firm, was first found suitable for use in devices such as portable phones and soon became popular in personal computers.  Initially, the BGA had a pin (bump) core distance of 1.5mm and a pin count of 225.  Now there are also a few LSI manufacturers are developing 500 pin BGA.  The problem with the BGA is the post-reflow appearance check.  American motorcycle ola enterprise with the model pressed into a natural resin tightly sealed package called MPAC, and the sealing method tightly sealed package called GPAC.  


2. C-(Ceramic)

A mark used to express the encapsulation of porcelain.  For example, CDIP stands for ceramic DIP.  It's a notation that's often used in practice.


3.COB(chip on board)

chip on board

chip on board

Chip on board encapsulation is one of the bare chip mount technologies. The semiconductor chip is attached to the printed circuit board, and the electrical joint between the chip and the substrate is successfully achieved by lead suture method, and the natural resin is used to cover the reliability.  Although COB is the simplest bare chip mount technology, its packaging density is far less than TAB and reverse welding technolog


4.DIP(dual in-line package)

1626761768(1).png

dual in-lin package

Double in-line package.  The pins are drawn from both sides of the package. The packaging materials are molecular compound plastic and porcelain pottery.  Europa semiconductor manufacturers use DIL.  DIP is the most popular plug-in package for applications ranging from standard thinking law IC, storage LSI, logo circuits, etc.  Pin core distance 2.54mm, pin number from 6 to 64.  Package width is generally 15.2mm.  Some packages with a width of 7.52mm and 10.16mm are called SK-DIP(Skinny Dual In-Line Package) and SL-DIP(Slim Dual In-Line Package) narrow-body DIP.  But most things are simply referred to collectively as DIP.  In addition, a ceramic DIP tightly sealed with low-melting glass is also called Cerdip.


4.1 DIC(Dual In-line Ceramic Package)  

Another name for a DIP(enclosed with glass) in ceramic enclosure.  

4.2 Cerdip:  

Glass - enclosed ceramic double - in-line package, used for ECL RAM, DSP(digital signal processor) circuits.  Cerdip with glass window is used for ultraviolet erasure type EPROM and logo circuit with EPROM inside, etc.  Pin core distance 2.54mm, pin number from 8 to 42.  In Toyo, this encapsulation is expressed as DIP-G(G for tightly enclosed glass).  

4.3 SDIP (Shrink Dual In-Line Package)  

Contraction DIP.  One of the cartridge packages, the same style as the DIP but smaller pin core distance (1.778mm) than the DIP(2.54mm)  

Hence the name.  The number of pins ranges from 14 to 90.  There are porcelain pottery and molecular compound plastic two kinds.  Also known as Sh-dip (Shrink Dual In-Line Package)  


5.flip-chip

1626762360(1).png

Reverse welding of the chip.  One of the bare chip packaging techniques in which metal bumps are made in the electrode area of an LSI chip and then bonded to the electrode area of a printed substrate by pressure welding.  The size of the occupied plane or object surface of the package is essentially the same as the chip size.  It is the smallest and thinnest of all encapsulation technologies.  But if the thermal expansion coefficient of the substrate is not the same as that of the LSI chip, the reaction will occur at the junction, so the reliability of the joint will be affected.  This is because the LSI chip must be reinforced with natural resin, and the use of the thermal expansion coefficient of the basic substrate material.  


6, FP (flat package)  

Flat package.  One of the externally mounted packages.  QFP or SOP(see QFP and SOP).  Local semiconductor manufacturers use this name as they see fit.  


7, H-(with heat sink)  

Represents the mark with radiator.  For example, HSOP stands for SOP with radiator.  


8, MCM(multi-chip module) multi-chip components  

1626762410(1).png

9, P - (plastic)  

A mark that expresses a molecular compound in a plastic package.  Such as PDIP expression of molecular compound plastic DIP.  


10, Piggy back  

Loaded package.  Porcelain ceramic package with socket, shape and DIP, QFP, QFN similar.  Used in the development of facilities with a logo for explicit recognition of the operation of reputation procedures.  For example, plug an EPROM into a socket to make adjustments.  This kind of package is basically fixed products, the market is not how circulation.  


11. QFP(Quad Flat Package) four-side pin flat package  

1626762525(1).png

Quad Flat Package


One of the externally mounted packages, the pins are drawn from the four sides in a seagull wing (L) shape.  Base material has porcelain pottery, metal and molecular compound plastic 3 kinds.  From the number of plastic packaging, molecular compounds accounted for the vast majority.  When there is no particular expression of the material, most things are the case for the molecular compound plastic QFP.  Molecular compound plastic QFP is the most popular multi-pin LSI package.  It is not only used in micro processor, door display and other digital thinking law LSI circuit, but also used in VTR signal disposal, audio signal disposal and other imitation LSI circuit.  Pin core distance 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm and other specifications.  Maximum number of pins in the 0.65mm core pitch specification is 304.  

Some LSI manufacturers to pin the core distance of 0.5mm QFP specifically known as contraction QFP or SQFP, VQFP.  But some manufacturers put the pin core distance of 0.65mm and 0.4mm QFP also known as SQFP, to make the name a little bit out of order.  

Additional QFPs with pin core distance of 0.65mm and body thickness of 3.8mm to 2.0mm are called MQFP(Metric Quad Flat Package) according to JEDEC(Electronic Facilities Council) standards.  55mm, 0.4mm, 0.3mm and other less than 0.65mm QFP is called QFP(FP) (QFP Fine Pitch), small core distance QFP.  Also called FQFP(Fine Pitch Quad Flat Package).  But now Toyo Electronics and Machinery Industry Association of the QFP shape specifications of the implementation of a new reputation.  There is no difference in the pin core distance, but according to the thickness of the packaging body, it is divided into three types: QFP(2.0mm ~ 3.6mm thick), LQFP(1.4mm thick) and TQFP(1.0mm thick).  

The disadvantage of the QFP is that the pin is prone to buckling when the pin core distance is less than 0.65mm.  To avoid pin distortions, several improved QFP varieties have emerged.  For example, a BQFP with a tree finger on the four corners of the package to mitigate the conflict pad (see 11.1);  GQFP with natural resin to try to take care of the ring covering the front end of the pin;  The TPQFP can be tested by setting the test bump in the package body and placing it in a special fixture to avoid pin deformation.  In terms of thinking rule LSI, many research and development products and highly reliable products are encapsulated in multi-layer ceramic QFP.  Products with a minimum pin core distance of 0.4mm and a maximum pin count of 348 are also available.  In addition to this, there is also a glass-enclosed ceramic QFP(see 11.9).  


11.1 BQFP(Quad Flat Package with Bumper)

1626762644(1).png

BQFP

our-side pin flat package with conflict mitigation pad.  One of the QFP packages, the four corners of the package body are provided with protrusions (conflict mitigation pads) to avoid pin buckling during transportation.  U.S. semiconductor manufacturers mainly use this package as appropriate in circuits such as microprocessors and ASICs.  Pin core distance is 0.635mm, and the number of pins ranges from 84 to about 196.  


11.2 QIC(Quad In-line Ceramic Package)  

Ceramic QFP of another name.  Name used as deemed appropriate by a local semiconductor manufacturer.  


11.3 QIP(Quad In-Line Plastic Package)  

Molecular compound plastic QFP another name.  Name used as deemed appropriate by a local semiconductor manufacturer.  


11.4 PFPF (plastic flat package)  

Molecular compound plastic flat package.  Molecular compound plastic QFP another name.  Name used as the local LSI manufacturer deems appropriate.  


11.5 QFH(Quad Flat High Package)  

 

1626762755(1).png

Four-side pin thick body flat package.  A molecular compound of plastic QFP, in order to avoid the packaging body disconnected, QFP body is made thicker.  Name used as deemed appropriate by a local semiconductor manufacturer.  


11.6 CQFP(Quad Fiat Package with Guard Ring)  

1626762878(1).png

Four-side pin flat package with best care ring.  Molecular compound plastic QFP, one of the pins with natural resin to try to take care of the ring masking, to avoid buckling deformation.  Before assembling the LSI on the printed substrate, cut the pins from the best care ring and make them into a seagull wing shape (L-style).  This kind of package in the United States motorcycle ola enterprise has mass production.  Pin core distance is 0.5mm, the number of pins is about 208 at most.  


11.7 MQUAD(metal quad)

1626762990(1).png

Olin Corporation of the United States developed a QFP package.  Substrate and cover are considered suitable and aluminum is used, tightly sealed with adhesive.  It can allow power of 2.5W ~ 2.8W under natural air cooling conditions.  Toyo new light electric industrial enterprise in 1993 to obtain the franchise production  


11.8 L - QUAD  

Porcelain pottery one of QFP.  Aluminum nitride for packaging substrate, base heat conductivity is 7 ~ 8 times higher than aluminum oxygen, with better heat dissipation.  The frame of the package is aluminum oxide, and the chip is tightly sealed by potting, thus limiting the cost.  It is a package developed for the thinking law LSI that allows W3 power under natural air cooling conditions.  The 208-pin (0.5mm core pitch) and 160-pin (0.65mm core pitch) LSI Mindrule packages have been developed and started mass production in October 1993.  


11.9 Cerquad  

1626763136(1).png

One of the external mount type package, that is, under the tightly closed ceramic QFP, used to encapsulate DSP and other thinking law LSI circuit.  Cerquad with Windows is used to encapsulate EPROM circuits.  The heat dissipation is better than the molecular compound plastic QFP, which can allow 1.5 ~ 2W power under the natural air cooling condition.  But the packaging cost is 3 ~ 5 times higher than the molecular compound plastic QFP.  Pin core distance is 1.27mm, 0.8mm, 0.65mm, 0.5mm0.4mm and other specifications.  The number of pins ranges from 32 to 368.


12. QFG (Quad Flat J-Leaded Package) four-side J-pin flat package    

1626763457(1).png

One of the externally mounted packages.  Pins are drawn from the four sides of the package in a downward J shape.  It is the name prescribed by Toyo Electronic Machinery Industry Association.  Pin core distance 1.27mm.  Material has molecular compound plastic and porcelain pottery two kinds.  

Molecular compound plastic QFJ most things called PLCC(Plastic Leaded Chip Carrier), used for logo, door display, DRAM, ASSP, OTP and other circuits.  Pin count from 18 to 84.  

Ceramic QFJ is also known as CLCC(ceramic leaded chip carrier) and JLCC(J-leaded chip carrier).  Windowed packages are used for ultraviolet erasure type EPROM and logo chip circuits with EPROM.  The number of pins ranges from 32 to 84.  


13. QFN(Quad Flat Non-Leaded Package)  

1626763495(1).png

Four-side pin free flat package, one of the externally mount packages, is used for high speed and high frequency IC packages.  It is now commonly known as the LCC.  QFN is the name prescribed by Toyo Electronic Machinery Industry Association.  The four sides of the package are equipped with electrode contacts, because there are no pins, the size of the mount occupies the plane or the surface of the object is smaller than that of QFP, and the height is lower than QFP.  However, when the initiation stress between the printed substrate and the package can not be relieved at the electrode contact.  Because this electrode contact is not easy to do as many as the QFP pins, generally from 14 to 100 or so.  

Material has porcelain pottery and molecular compound plastic two kinds.  When marked with LCC, it is mostly ceramic QFN.  Core distance of electrode contact is 1.27mm.  Molecular compound plastic QFN is a kind of low cost encapsulation of glass epoxy gas natural resin printed substrate.  In addition to the core distance of electrode contact 1.27mm, there are two kinds of 0.65mm and 0.5mm.  This encapsulation is also known as molecular compound plastic LCC, PCLC, P-LCC, etc. 


13.1 PCLP(Printed Circuit Board Leadless Package)  

Printed circuit board leadless package.  Toyo Fujitsu Corporation to molecular compound plastic QFN(molecular compound plastic LCC) as deemed appropriate to use the name.  Pin core distance is 0.55mm and 0.4mm in two specifications.  So far it is in the development stage.  


13.2 P-LCC(Plastic Teadless Chip Carrier)(Plastic Leaded Chip Currier)  

Sometimes it's the molecular compound plastic QFJ, sometimes it's QFN(molecular compound plastic LCC) (see QFJ and QFN).  Local LSI manufacturers use PLCC to express the package with lead and P-LCC to express the package without lead to show the difference.  


14. QFI(Quad Flat I-Leaded Packgage) four-side I-pin flat package  

One of the externally mounted packages.  Pins are drawn from the four sides of the package, downward to the I word.  Also known as MSP(Mini Square Package).  Placement and printing substrate for joint welding.  Because the pin has no part of the tip, the mount occupies the plane or the size of the object surface is less than QFP.  Hitachi Manufacturing developed and used this package for video file imitation IC.  In addition, Toyo Motorola's PLL IC also saw fit to use this package.  Pin core distance 1.27mm, pin number from 18 to 68.  


15.TCP(Tape Carrier Package) membrane encapsulation TCP technology   

Tape Carrier Package

TCP

Mainly used on Intel Mobile Pentium MMX.  CPUs that use TCP packaging as appropriate are much smaller in calories than normal PGA pin array CPUs, which can be used in laptops to reduce the size of the add-on radiator and increase the space utilization of the host, which is more common in a few ultra-laptop computers.  But because TCP encapsulation is the CPU directly welded to the motherboard, because the average user is not easy to change. 


 15.1 DTCP(Dual Tape Carrier Package)  

Double pin with load package.  One of TCP(encapsulation with load).  Pins are manufactured on an insulating strip and are drawn from both sides of the package.  Because of TAB(semi-automatic on-load soldering) technology, the package is very thin.  It is often used to drive LSI by liquid crystal exposure, but most of them are custom products.  

In addition, a 0.5mm thick LSI book package for storage is under development.  In Toyo, in accordance with EIAJ(Toyo Electronic Machinery Industry) standards, DTCP is named as DTP.  


15.2 QTCP(Quad Tape Carrier Package)  

Four-side pin with load package.  One of the TCP packages that form pins on the insulation strip and exit from the four sides of the package.  Is the use of TAB technology thin packaging.  In Toyo, it is called QTP(Quad Tape Carrier Package).  


15.3 Tape Automated Bonding (TAB) Tape semi-automatic Bonding technology  

1626763806(1).png

Tape Automated Bonding (TAB) semi-automatic Bonding is a kind of Chip (Chip) with multiple connecting feet of large scale integrated circuit (IC), which no longer uses the traditional packaging to become a complete individual, but uses TAB carrier, and directly glue the unsealed Chip on the board surface.  The soft 'Polyimide' tape and the inner and outer pins etched by copper foil are used as the carrier, so that the large chip is attached to the inner pin first.  After semi-automatic testing, the assembly is completed by engaging the circuit board with 'external pins'.  This packaging and assembly of a new construction method, namely known as TAB method. 


16、PGA(pin grid array)

1626763890(1).png

PGA

Display pin package.  One of the cartridge packages in which the straight pins on the bottom face are arranged in a display pattern.  The packaging substrate is generally considered appropriate and multilayer ceramic substrate is used.  In the case where the material name is not specifically expressed, most are ceramic PGA, used for high-speed large-scale thinking law LSI circuits.  The cost is high.  Pin core distance is generally 2.54mm, pin length is about 3.4mm, the number of pins from 64 to about 447.  In order to reduce the cost, the packaging substrate can be replaced by glass epoxy gas natural resin printing substrate.  

There are also 64 to 256 pin molecular compounds of plastic PGA.  In addition, there is a pin core distance of 1.27mm, pin length of 1.5mm~2.0mm short pin surface mount type PGA(touch welding PGA), half smaller than the insertion type PGA, so the packaging body can be made not very large, and the number of pins than the insertion type (250 ~ 528).


17、LGA(land grid array)

LGA

LGA

Contact display package.  That is, a package with an array of tank electrode contacts is made on the bottom side.  Just plug it into the socket for assembly.  The ceramic LGA with 227 contacts (1.27mm core distance) and 447 contacts (2.54mm core distance) has been applied to high-speed thinking rule LSI circuits.  The LGA, in contrast to the QFP, can accommodate more input and output pins in a smaller package.  In addition, the lead is suitable for high speed LSI because of its low impedance.  


18. Lead packaging on the chip  

LSI packaging technology, a structure in which the front end of the lead frame is placed above the chip, and a convex solder joint is manufactured near the core of the chip, and the lead is sutured for electrical co-programming.  In contrast to the original structure where the lead frame was placed near the side of the chip, the width of the chip can be about 1mm in a package of the same volume.  


19, Quip (Quad In-Line Package)   

1626764003(1).png

The Quad In-Line is a four-pin in-line package called the Quill.  Pins are drawn from both sides of the package and flexed down into four rows at intersecting intervals.  The pin core distance is 1.27mm, and when inserted into the printing substrate, the core distance becomes 2.5mm.  Because this works for standard printed circuit boards.  Is a smaller package than the standard DIP.  Toyo Electric Corporation has used some packages as appropriate in its logo chips for desktop computers and home appliance products.  Material has porcelain pottery and molecular compound plastic two kinds.  Pin count 64.  


20. SOP(Small Out-Line Package)  

Small shape package.  One of the externally mounted packages, the pins are drawn from both sides of the package in the shape of a seagull wing (L shape).  Material has molecular compound plastic and porcelain pottery two kinds.  Also known as SOL(Small Out-Line L-Leaded Package), DFP(Dual Flat Package), SOIC(SmallOut-Line Integrated Circuit), DSO(Dual Small)  Out-lint) many overseas semiconductor manufacturers use this name as they see fit.  

SOP is not only used in memory LSI, but also widely used in small scale ASSP circuits.  SOP is the most popular surface-mount package in the field where the input and output terminals do not exceed 10 to 40.  Pin core distance 1.27mm, pin number from 8 to 44.  

As the SOP progresses, it is gradually delivered:  

 

SSOP with pin core distance less than 1.27mm (from large to small SOP);  

The assembly height is less than 1.27mm TSOP(thin small shape package);  

VSOP(Very Small Form Package);  TSSOP(Thin from Large to Small SOP);  

SOT(small shape junction transistor);  SOP with heat sink is called HSOP;  

Local semiconductor manufacturers call the SOP without radiator Fin SONF(Small out-of-line non-fin);  

Local manufacturers call wide-body SOP (Wide-Jype) SOW  

 

21. MFP(mini flat package) small shape flat package   

1626764088(1).png

Molecular compound plastic SOP or SSOP alias.  Name used as deemed appropriate by a local semiconductor manufacturer. 


22、SIMM(single in-line memory module) 

1626764341(1).png

Single row storage assembly.  A storage assembly equipped with electrodes only near one side of a printed substrate.  Generally refers to a component that plugs into a socket.  The standard SIMM is available with a 30 electrode with a core pitch of 2.54mm and a 72 electrode with a core pitch of 1.27mm.  SIMM with 1 and 4 megabytes of DRAM encapsulated with SOJ on one or both sides of printed substrate has been widely used in private computers, office stations and other facilities.  At least 30 to 40 percent of DRAM is assembled in SIMM.  


23, DIMM(Dual Inline Memory Module  

1626764442(1).png

It is very similar to SIMM, except that the two ends of the golden fingers of DIMM do not communicate with each other as SIMM does. Instead, the two ends of the golden fingers of DIMM communicate with each other independently, because this can satisfy the transmission needs of a larger number of data signals.  The same think appropriate and use DIMM, SDRAM interface and DDR memory interface is also slightly different, SDRAM DIMM is 168PIN DIMM structure, gold finger each side is 84PIN, gold finger head has two cards, used to prevent inserted into the slot, the memory is not correctly inserted into the reverse and caused by burning destruction;  DDR DIMM considers it appropriate to use the 184PIN DIMM structure, with 92PIN on each side of the golden finger and only one bayonet on the head of the golden finger.  The number of bayonets is not the same, is the most superficial difference between the two.  

DDR2 DIMM is 240PIN DIMM structure, and each side of the golden finger has 120PIN. Just like DDR DIMM, there is only one card on the head of the golden finger, but the position of the card is slightly different from that of DDR DIMM, because the DDR memory cannot insert DDR2 DIMM.  DDR2 memory can not be inserted into DDR DIMM, because the motherboard with both DDR DIMM and DDR2 DIMM at one point, will not show the problem of memory inserted into the wrong slot.  


24, SIP(Single In-Line Package)  

SIP

Single in-line package.  Most European semiconductor manufacturers use the name SIL (Single In-Line) as they see fit.  Pins are drawn from one side of the package and arranged in a straight line.  The package is in a lateral position when assembled on a printed substrate.  Pin core distance is generally 2.54mm, the number of pins from 2 to 23, most are custom products.  Packaging styles vary.  Some also refer to the same style as ZIP package as SIP.  


25. SMD(Surface Mount Devices)  

 

SMD

SMD chip

Appearance-mounted parts.  Occasionally, some semiconductor manufacturers classify SOP as SMD.  


26. SOI(Small Out-Line I-Leaded Package)  

I pin small shape package.  One of the externally mounted packages.  Pins are drawn from both sides of the package in a downward I shape with a core distance of 1.27mm.  The mount occupies a plane or surface of an object smaller than the SOP.  Hitachi used this package as deemed appropriate in the imitation IC(motor drive embezzlement IC).  Pin count 26.  


27. SOJ(Small Out-Line J-Leaded Package) 

SOJ

J - pin small shape package.  One of the externally mounted packages.  The pins lead down from both sides of the package in a J shape, hence the name.  It is generally made of molecular plastics, mostly used in memory LSI circuits such as DRAM and SRAM, but mostly DRAM.  Many DRAM components packaged in SOJ are assembled on SIMM.  Pin core spacing is 1.27mm, with pin counts ranging from 20 to 40(see SIMM).  


28, To PackageTo

To PackageTo

To PackageTo

Its chassis is a piece of circular metal plate, and then put a small piece of glass and heating, the glass melt after the lead is fixed in the hole, the hole and the lead is called the combination of head seat, so first in the head seat on the head gold-plated, because the bottom of the integrated circuit slice is gold-plated, so can be welded by gold, germanium welding wax;  When welding, the head seat is preheated, so that the welding wax placed there is absolutely molten, and then the circuit slice is placed on the welding wax, and the two form a good combination after cooling.