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Selection of surface mount components in SMT

 I. Overview

The selection and design of surface-mounted components is a key part of the overall product design. The designer determines the electrical performance and function of the components in the system structure and detailed circuit design stage. In the smt design stage, it should be based on the specific conditions and overall situation of the equipment and process. The design requirements determine the packaging form and structure of surface mount components. Surface-mounted solder joints are both mechanical connection points and electrical connection points. A reasonable choice will have a decisive impact on improving PCB design density, productivity, testability and reliability.


  Surface mount components are no different in function from plug-in components, and the difference lies in the packaging of the components. Surface-mounted packages must withstand high milk temperatures during soldering, and their components and substrates must have matching thermal expansion coefficients. These factors must be fully considered in product design.

The main advantages of choosing a suitable package are: 1). Effectively save PCB area; 2). Provide better electrical performance; 3). Protect the internal components from humidity and other environmental influences; 4). Provide good communication links; 5). Help heat dissipation and provide convenience for transmission and testing.

   2. Selection of surface mount components

  Surface mount components are divided into two categories: active and passive. According to the shape of the pin, it is divided into gull wing type and "J" type. The following describes the selection of components in this category.

  1 Passive device

  The source devices mainly include monolithic ceramics, tantalum capacitors and thick film resistors, and the shape is rectangular or cylindrical. Cylindrical passive components are called "MELF". They are prone to rolling when reflow soldering. Special pad design is required and should generally be avoided. Rectangular passive components are called "CHIP" chip components. They are small in size, light in weight, antimicrobial impact and shock resistance, and low parasitic loss. They are widely used in various electronic products. In order to obtain good solderability, the electroplating of the nickel barrier layer must be selected.

  Surface mount resistor capacitors are packaged in various dimensions. When choosing, avoid choosing too small size: <0.08 inch X 0.05 inch to reduce the difficulty of placement, and avoid choosing too large size:> 0 inch X 0.12 inch to avoid using epoxy glass substrate FR-4 Chip components that produce a coefficient of thermal expansion (CTE) mismatch are required to withstand a soldering time of 5-10S at a temperature of 260°C.

  (1) Chip resistor

   Chip resistors are divided into two categories: thick film type and thin film type. The rated power is 1/16, 1/8, 1/4 watts, and the resistance value is from 1 ohm to 1 megohm. There are various sizes and specifications. According to the external size, it is divided into 0805 (0.08 inches X 0.05 inches) , 1206 (0.12 inches X 0.06 inches), 1210 (0.12 inches X 0.10 inches), etc. Generally, 1/16, 1/8, and 1/4 watt resistors correspond to 0805, 1206, and 1210. When selecting, 1/8 watts and 1206 external dimensions should be the first choice.

  (2) Ceramic capacitor

   Ceramic capacitors have three different dielectric types: COG or NPO, X7R and Z5U. Their capacitance ranges are different. COG or NPO is used for circuits with high stability in a wide range of temperature, voltage and frequency; X7R and Z5U dielectric capacitors have poor temperature and voltage characteristics and are mainly used in bypass and decoupling applications.

  Ceramic capacitors are prone to cracking during wave soldering due to CTE mismatch. During welding, the CTE of the electrode and the terminal joint is high, and the heating is faster than that of the ceramic, which causes the mismatch to produce cracks. The solution is to preheat the circuit board before wave soldering to reduce thermal shock. Z5U ceramic capacitors are easier to crack than X7R capacitors, so X7R capacitors should be used as much as possible when choosing. Like chip resistors, 1206 capacitors should be selected for their external dimensions.

  (3) Resistance network

  The surface mount resistor network adopts "SO" package, and the pins are Euro-wing shape. The design standard of the pad pattern can be selected according to the needs of the circuit.

  The current common external dimension standards are as follows: 150MIL wide shell (SO) has 8, 14, 16 pins;

   220MIL wide shell (SOMC) has 14, 16 pins; 300MIL wide shell (SOL) has 14, 16, 20, 24, 28 pins.

  (4) Tantalum capacitor

  Surface mount tantalum capacitors have extremely high volumetric efficiency and high reliability. At present, this component lacks standardization and generally uses alphabetic marks.

  The main reason for choosing tantalum capacitors is to pay attention to the structure of the terminals at both ends. It has two main structural forms: one is non-pressing film type, one end is welded with short film contacts; the other is plastic film type, pin contacts are rolled down. Due to the mobility of the patch, the problem of inaccurate patching occurs when grabbing non-pressing film capacitors, and the metal terminal joints of this type of capacitor will make the solder joints brittle, and plastic film tantalum capacitors should be used as much as possible when selecting.

  2, active device

   There are two types of surface mount chip carriers: ceramics and plastics.

  The advantages of ceramic chip packaging are: 1) Good airtightness and good protection for the internal structure 2) Short signal path, significantly improved parasitic parameters, noise, and delay characteristics 3) Reduce power consumption. The disadvantage is that because the leadless absorbs the stress generated when the solder paste melts, the CTE mismatch between the package and the substrate can cause solder joints to crack during soldering. At present, the commonly used ceramic wafer carrier is the leadless ceramic conventional wafer carrier LCCC.

  Plastic packaging is currently widely used in the production of military and civilian products, and has a good cost performance. Its packaging forms are divided into: small outline transistor SOT; small outline integrated circuit SOIC; plastic package leaded chip carrier PLCC; small outline J package; plastic flat package PQFP.

   In order to effectively reduce the PCB area, SOIC with a pin count of less than 20, PLCC with a pin count between 20-84, and a PQFP with a pin count greater than 84 are preferred when the device functions and performance are the same.

  2.2.1 Leadless ceramic chip carrier LCCC

   There are two types of electrode center distance: 1.0mm and 1.27mm. The rectangle has 18, 22, 28, 32 electrodes; the square has 16, 20, 24, 28, 44, 56, 68, 84, 100, 124, 156 electrodes. Since most of the substrates currently used are FR-4, the CTE mismatch is more serious and should be avoided as much as possible.

   2.2.2 Small outline crystal is SOT after all

  The commonly used packaging forms are three-pin SOT23, SOT89, and four-pin SOT143, which are generally used for diodes and triodes.

  SOT23 is a commonly used three-pin package. The large chip size that can be accommodated is 0.030 inches X 0.030 inches. It is divided into low, middle, and high positions according to the section height. In order to obtain a better cleaning effect, high-level packaging is generally preferred.

  SOT89 is generally used for devices with higher power, and the large chip size that can be accommodated is 0.060 inches X 0.060 inches.

   SOT143 is usually used in the case of radio frequency (FR) transistors, and the large chip size that can be accommodated is 0.025 inches X 0.025 inches.

   2.2.3 Small outline integrated circuit SOIC

  Using European wing-shaped package. For devices with no more than 20 pins, this type of package can save more coverage area.

   SOIC package mainly has two different shell widths: 150MIL and 300MIL, mainly with 8, 14, 16, 20, 24, 28 pin numbers.

   When selecting, it should be noted that the coplanarity of the pins is as large as 0.004 inches.

   2.2.4 Plastic Flat Package PQFP

  Using European wing-shaped package. Mainly used in ASIC application specific integrated circuits. The pin center distance is divided into 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.3mm, and the number of pins is 84-304.

  The smaller the pin center distance and the more pins, the more easily the pins will be damaged, and the coplanarity will not be easily maintained within 0.004 inches. When selecting, you should try to use the corner cushion pad package (there are four pads about 2MIL longer than the pins) in order to protect the pins during installation, rework, and testing.

   2.2.5 Plastic package leaded chip carrier PLCC and small outline J package

   are all in J-shaped package. With plasticity, it can absorb the stress of the solder joints to avoid cracking of the solder joints and form a good solder joint.

   PLCC is used when the number of pins is greater than 40, which occupies a small coverage area, is not easy to deform, and has good coplanarity.

   PLCC is divided into rectangular and square according to its shape. The number of rectangular leads is 18, 22, 28, and 32; the number of square leads is 16, 20, 24, 28, 44, 52, 68, 84, 100, 124, and 156.

  Small-outline J package is a hybrid form of SOIC and PLCC, which combines the advantages of PLCC's high lead strength, good coplanarity and high SOIC space wire retention rate. Mainly used for high-density DRAM (1 and 4MB).

   Three, Euro-wing package and J-shaped package device pin analysis and comparison

   The shape of the pin determines the solder joints formed, which has an important influence on the reliability and productivity of the product. The two main shapes currently used are: Euro-wing shape and J-shape, which form the solder joints.