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Design of high-precision and high-speed A/D converter clock stabilization circuit for PCB proofing

 The main function of the pcb proofing data converter is either to generate analog waveforms from regular time sampling, or to generate a series of regular time samples from an analog signal. Therefore, the stability of the sampling clock is very important. From the point of view of the data converter, this instability (that is, random clock jitter) will cause uncertainty in when the analog-to-digital converter samples the input signal. In high-speed systems, the timing error of the clock or oscillator waveform will limit the maximum rate of a digital I/O interface. Not only that, it will also increase the bit error rate of the communication link, and even limit the A/D converter. (ADC) dynamic range, in order to obtain the best performance of the data converter, it is extremely important to properly select the sampling and encoding clock.


PCB proofing ADC circuit

In recent years, foreign research on high-speed A/D converters has been the most active, and some improved structures have appeared in the basic Flash structure [2], such as subranging circuit structures (such as half-flash structure, Pipelined, Multistage structure, Multistep structure). In fact, they are a circuit structure composed of multiple Flash circuit structures and other functional circuits in different forms. This structure can make up for the shortcomings of the basic Flash circuit structure and realize high-speed, high-resolution A/D converters. This kind of structure is gradually replacing the long-standing SAR and integral structure, and there is also a type of bit-per-stage circuit structure. Further improvement on the basis of it, you will get a A circuit structure called Folding (also called Mag Amps structure) This is a Gray code serial output structure. These circuit design techniques are the development of high-speed, high-resolution, and high-performance A/D converters. Played a positive role in promoting.

In addition, in the high-resolution A/D converter circuit design technology, the sigma-delta circuit structure is currently a very popular circuit design technology. This circuit structure is not only used in high-resolution low-speed or medium-speed A/D converters. Will gradually replace the SAR and integral circuit structure, and this structure combined with the pipeline structure, is expected to achieve higher resolution, and higher speed A/D converter.

PCB proofing clock duty cycle stabilization circuit

With the continuous expansion and performance improvement of electronic systems in weapons and equipment in the new era, the complexity of electronic systems is also increasing. In order to ensure the capabilities and performance of data sampling, control feedback, and digital processing of electronic systems, modern military electronic systems The requirements for A/D converters are also getting higher and higher, especially for military data communication systems and data acquisition systems. The demand for high-speed and high-resolution A/D converters is increasing. The clock duty cycle stabilization circuit is used as a high-speed , The core unit of the high-precision A/D converter plays a vital role in the performance of the converter’s signal-to-noise ratio (SNR) and effective bit (ENOB). Therefore, it is necessary to ensure the high-speed, high-precision A/D converter For performance, it is necessary to ensure that the sampling and encoding clock has a suitable duty cycle and small jitter. Therefore, it is very necessary to carry out research on the clock duty cycle stabilization circuit.

Since the clock duty cycle stabilization circuit is the core unit of high-speed, high-precision A/D converters, and there are almost no products with separate clock duty cycle stabilization circuits, it is only reported in high-speed, high-precision A/D converters. Compared with the products of other companies, ADI's products can improve the sampling performance mainly due to the improvement of the DCS (duty cycle stabilizer) circuit. The DCS circuit is responsible for reducing the jitter of the clock signal, and the sampling timing depends on the clock. Signals, the previous DCS circuits of various companies can only control the jitter to about 0.25ps, while the new high-performance products AD9446 and LTC2208 can reduce the jitter to about 50fs. Generally, reducing the jitter can improve the SNR, thereby increasing the effective resolution ( ENOB: effective number of bits), and can achieve a sampling rate of more than 100Msps while reaching a 16-bit quantization number. If the sampling rate is increased without controlling the jitter, the ENOB will be reduced and the desired resolution cannot be obtained. It is impossible to increase the number of quantization bits. With the development of high-performance A/D converters, DCS circuits can develop in the direction of higher speed, less jitter and stability. Table 1 lists the clock duty in foreign A/D converters. The main technical and parameter indicators of the stable circuit.

In fact, so far, AD's 60fs jitter has been the smallest. Now the aperture jitter is generally controlled at about 1 ps, and jitter higher than this number or even tens of ps is actually of little significance.

Realization method of pcb proofing clock stabilization circuit

From the current research situation at home and abroad, the clock circuit used to stabilize the high-speed ADC is mainly a phase-locked loop (Phase-locked loop, PLL). The phase-locked system is essentially a closed-loop phase control system. Simply put, it is a circuit that can synchronize the output signal with the input signal in terms of frequency and phase, that is, after the system enters the locked state (or synchronized state), The phase difference between the output signal of the oscillator and the input signal is zero or remains constant. Because the phase-locked loop has many excellent characteristics, it can be widely used in high-performance processor clock generation and distribution, system frequency synthesis and conversion, and automatic Frequency tuning tracking, bit synchronization extraction in digital communication, phase lock, phase lock frequency multiplication and frequency division, etc.

This article proposes a delay-locked loop DLL (Delay-locked loop DLL) design. In fact, the PLL mainly uses the phase detector and filter to monitor the feedback clock signal and the input clock signal, and then use the generated voltage difference Control the voltage-controlled oscillator to generate a signal similar to the input clock, and finally achieve the purpose of frequency locking. The function of the DLL is to insert a delay pulse between the input clock and the feedback clock until the rising edges of the two clocks are aligned, and When synchronization is achieved, when the input clock pulse edge and the feedback pulse edge are aligned, the on-chip delay phase-locked loop DLL can all be locked. After the clock is locked, the circuit is no longer adjusted and there is no difference between the two clocks. In this way, the on-chip delay phase-locked loop uses the DLL output clock to compensate for the time delay caused by the clock distribution network, thereby effectively improving the clock source and load. Time delay between. First of all, the delay line is less affected by noise than the oscillator. This is because the damaged zero-crossing point in the waveform disappears at the end of the delay line and recirculates in the oscillator circuit, thus generating more Secondly, the delay time is rapidly changed within the control voltage change in the DLL, that is, the transfer function is simply equal to the gain KBCDL of the VCDL. In short, the oscillator used in the PLL has instability and phase offset Accumulation, when the compensation clock separately causes time delay in the network, it tends to reduce the performance of the PLL. Therefore, the stability and stable speed of the DLL are better than the PLL.

◇The overall circuit structure design of pcb proofing

The overall structure of the clock duty cycle stabilization circuit is shown in the dashed box in Figure 1. It consists of an input buffer amplifier A, switches K1, K2 and a delay-locked loop (DLL).

When the sampling clock frequency is lower than the lower limit of the working limit of the DLL, the switches K1 and K2 are closed upwards and the DLL is bypassed; when the switches K1 and K2 are closed downwards, the DLL starts to function and adjusts the phase of the input clock signal to make the input clock The duty cycle is close to 50%, and the jitter is less than 0.5ps.

◇PCB proofing delay phase-locked loop (DLL)

The structure of the delay-locked loop (DLL) is similar to the ordinary phase-locked loop (PLL), except that it uses a voltage-controlled delay line (VCDL, Voltage Control Delay Line) instead of the voltage-controlled oscillator . Its structure diagram is shown in Figure 2. A common DLL includes 4 main modules: phase detector, charge pump circuit, loop filter and VCDL. The voltage-controlled delay line is an open-circuit chain formed by a series of voltage-controlled delay variable power supplies in series, and its output signal is the delay ntd of the input signal. The input and output of the voltage-controlled delay line are sent to the phase detector for comparison, and the phase difference between the two is locked at one cycle (in-phase comparison) or half cycle (inverted comparison) through the phase-locked loop, then each delay The delay time of the unit is T/n or T/2n, where n is the number of stages of delay.

The function of the phase detector in DLL is to identify the phase error and adjust the error of the charge pump to control the output frequency of the voltage oscillator. The common phase detector characteristics are cosine, sawtooth and triangle. The phase detector can be divided into There are two types of analog phase detectors and digital phase detectors. The main indicators are:

(1) Phase detection characteristic curve. That is, the output voltage of the phase detector varies with the phase difference of the input signal. This characteristic requires that it be linear and have a large linear range.

(2) Phase detection sensitivity. That is, the output voltage generated by the unit phase difference, the unit is v/raJ. The phase discrimination sensitivity of an ideal phase detector should have nothing to do with the amplitude of the input signal. When the phase discrimination characteristic is nonlinear, it is generally defined as the sensitivity at the point Pt=0.

(3) Phase discrimination range, that is, the phase range where the output voltage changes monotonously with the phase difference.

(4) The operating frequency of the phase detector.

The charge pump in DLL is actually a charge switch, which can convert the phase difference and lead lag into current, and then convert it into a control voltage through the integral action of the first-order capacitor, and then use this feedback control voltage to control the delay time. In order to achieve the required phase delay.

The DLL has two functions: one is to detect the duty cycle; the other is to detect the clock jitter. Since the delay lock is 50% of the clock cycle, when the phase detector (PDF) detects that the duty cycle is greater than 50%, the charge The pump (CP) goes up to decrease the duty cycle, and vice versa, goes down to increase the duty cycle.

The above is an introduction to the design of high-precision and high-speed A/D converter clock stabilization circuit for PCB proofing. Ipcb is also provided to PCB manufacturers and PCB manufacturing technology