Ultra-precision PCB Fabrication, High Frequency PCB, High Speed PCB, IC Substrate, Multilayer PCB and PCB Assembly.
The most reliable PCB custom service factory.
PCB News

PCB News

PCB News

PCB News

Precautions for designing high-speed circuit boards for PCB proofing
2021-10-03
View:22
Author:Kavie

 PCB Proofing I recently wrote a letter about an article about PCB characteristic impedance. This article explains how changes in the process cause the actual impedance to change, and how to use accurate field solvers to predict this phenomenon. I pointed out in the letter that even if there is no process change, other factors will cause the actual impedance to be very different. When designing high-speed circuit boards, automated design tools sometimes fail to find this unobvious but very important problem. However, as long as some measures are taken in the early steps of the design, this problem can be avoided. I call this technique "defensive design".

 PCB


PCB proofing stacking number problem
A good laminated structure is the best preventive measure for most signal integrity problems and EMC problems, and it is also the most misunderstood by people. There are several factors at play here, and a good way to solve one problem may worsen other problems. Many system design vendors will suggest that there should be at least one continuous plane in the circuit board to control the characteristic impedance and signal quality. As long as the cost can be affordable, this is a good suggestion. EMC consultants often recommend placing a ground fill or ground layer on the outer layer to control electromagnetic radiation and sensitivity to electromagnetic interference. This is also a good suggestion under certain conditions.
However, due to transient currents, this method may be troublesome in some common designs. First, let's look at the simple case of a pair of power plane/ground plane: it can be seen as a capacitor .It can be considered that the power layer and the ground layer are the two plates of the capacitor. To get a larger capacitance value, it is necessary to move the two plates closer (distance D) and increase the dielectric constant (εr). The larger the capacitance, the lower the impedance, which is what we want because it can suppress noise. No matter how the other layers are arranged, the main power layer and the ground layer should be adjacent and in the middle of the stack. If the distance between the power layer and the ground layer is large, it will cause a large current loop and bring a lot of noise. For an 8-layer board, placing the power layer on one side and the ground layer on the other side will cause the following problems:
1. The greatest crosstalk. Due to the increase in the mutual capacitance, the crosstalk between the signal layers is greater than the crosstalk of the layers themselves.
2. The largest circulation. Current flows around the power planes and parallel to the signal, a large amount of current enters the main power plane and returns through the ground plane. The EMC characteristics will deteriorate due to the increase of the circulating current.
3. Loss of control over impedance. The farther the signal is from the control layer, the lower the accuracy of impedance control due to other conductors around it.
4. Because it is easy to cause solder short circuit, it may increase the cost of the product.
We must make a compromise choice between performance and cost. For this reason, I am here to talk about how to arrange the digital circuit board to get the best SI and EMC characteristics.
The distribution of each layer of the PCB is generally symmetrical. In my humble opinion, more than two signal layers should not be placed next to each other; otherwise, the control over SI will be largely lost. It is best to place the internal signal layers symmetrically in pairs. Unless some signals need to be wired to SMT devices, we should minimize the signal wiring on the outer layer.
For circuit boards with more layers, we can repeat this placement method many times .It is also possible to add additional power layers and ground layers; as long as it is ensured that there is no pair of signal layers between the two power layers.
The wiring of high-speed signals should be arranged in the same pair of signal layers; unless this principle has to be violated due to the connection of SMT devices. All traces of a signal should have a common return path (that is, the ground plane). There are two ideas and methods to judge what two layers can be regarded as a pair:
1. Ensure that the return signals at equal distances are exactly the same. This means that the signals should be routed symmetrically on both sides of the internal ground plane. The advantage of this is that it is easy to control the impedance and circulating current; the disadvantage is that there are many vias on the ground layer, and there are some useless layers.
2. Two signal layers of adjacent wiring. The advantage is that the vias in the ground layer can be controlled to a minimum (using buried vias); the disadvantage is that the effectiveness of this method is reduced for some key signals.
I like to use the second method. It is preferable that the ground connection for element driving and receiving signals can be directly connected to the layer adjacent to the signal wiring layer. As a simple wiring principle, the surface wiring width in inches should be less than one-third of the drive rise time in nanoseconds (for example, the wiring width of high-speed TTL is 1 inch).
If it is powered by multiple power supplies, a ground layer must be laid between the power supply wires to separate them. Do not form a capacitor, so as not to cause AC coupling between the power supplies.
The above-mentioned measures are all in order to reduce the circulation and crosstalk, and strengthen the impedance control ability. The ground plane will also form an effective EMC "shielding box". Under the premise of considering the influence on the characteristic impedance, the unused surface area can be made into a ground layer.