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Boundary-Scan of ICT technology
2021-10-11
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Author:Aure

Boundary-Scan of ICT technology



In eighty to ninety percent of circuit board manufacturers, ICT testers require at least one test point for each circuit node. However, as the integration of devices increases, the functions are getting stronger, the package is getting smaller and smaller, the number of SMT processing components increases, the use of multi-layer boards, and the increase of PCBA board component density, it is necessary to put a probe at each node It becomes very difficult. In order to increase the test points, the manufacturing cost is increased; at the same time, it becomes difficult to develop a test library of powerful devices, and the development cycle is prolonged. To this end, the Joint Test Organization (JTAG) promulgated the IEEE1149.1 test standard.

 

IEEE1149.1 defines several important characteristics of a scanning device. Firstly, the four (five) pins that make up the test access port (TAP) are defined: TDI, TDO, TCK, TMS, (TRST). The test mode selection (TMS) is used to load control information; secondly, the TAP controller is defined Several different test modes are supported, mainly external test (EXTEST), internal test (INTEST), and running test (RUNTEST); finally, the boundary scan language (Boundary Scan Description Language) is proposed, and the BSDL language describes important information of scanning devices. It defines the pins as input, output and bidirectional types, and defines the TAP mode and instruction set.

 


Boundary-Scan of ICT technology


Each pin of a device with boundary scan is connected to a unit of a serial shift register (SSR), called a scan unit. The scan units are connected together to form a shift register chain, which is used to control and detect device leads. foot. Its specific four pins are used to complete the test task.

 

Connect the scan chains of multiple scan devices through their TAPs to form a continuous boundary register chain. Adding a TAP signal at the head of the chain can control and detect all the pins of the devices connected to the chain. This kind of virtual contact replaces the physical contact of the needle bed fixture to each pin of the device, and the virtual access replaces the actual physical access, removing a large amount of test pads occupying the PCB board space, and reducing the manufacturing cost of the PCB and the fixture.

 

As a test strategy, when designing the PCB for testability, special software can be used to analyze circuit points and devices with scanning functions to determine how to effectively place a limited number of test points without reducing test coverage. The most economical way to reduce test points and test pins.

 

Boundary scan technology solves the difficulty of not being able to increase test points. More importantly, it provides a simple and fast method to generate test patterns. Using software tools, BSDL files can be converted into test patterns, such as Teradyne’s Victory and GenRad’s Basic Scan and Scan Path Finder. Solve the difficulty of writing complex test libraries.

 

The TAP access port can also be used to implement online programming (In-System Program or On Board Program) such as CPLD, FPGA, and Flash Memroy.


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