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Tips for writing PCB design rule checker
PCB News
Tips for writing PCB design rule checker

Tips for writing PCB design rule checker

2021-11-05
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Author:Kavie

This article describes a method of writing a PCB design rule checker (DRC) system. After obtaining the PCB design using the circuit diagram generation tool, you can run DRC to find any failures that violate the design rules. These operations must be completed before the start of subsequent processing, and the developer of the development circuit diagram generation tool must provide most designers can easily master the DRC tool.


PCB


Writing your own PCB design rule checker has many advantages. Although the design checker is not that simple, it is not unattainable, because any designer familiar with existing programming or scripting languages can fully design the checker. The advantage of this work is inestimable.
However, general-purpose tools sold on the market often do not have enough flexibility to meet specific design needs. Therefore, the customer must reflect the new feature requirements to the DRC tool developer, and this usually requires a certain amount of money and time, especially when the requirements are constantly updated. Fortunately, most tool developers can provide customers with a convenient way to write their own DRC to meet specific needs. However, this powerful tool has not yet been widely recognized or used. This article provides a practical guide for using DRC tools to get the most benefit.
Since DRC must traverse the entire circuit diagram of the PCB design, including each symbol, each pin, each net, and each attribute, an unlimited number of "attached" files can be created if necessary. As described in Section 4.0, DRC can indicate any minor deviations that violate the design rules. For example, one of the attached files may contain all decoupling capacitors used in the design. If the number of capacitors is lower or higher than the expected value, a red mark will be marked in the place where the power line dv/dt problem may occur [1]. These ancillary files may be necessary, but not any commercial DRC tool can necessarily create these files.
Another advantage of DRC is that it is easy to update to meet the needs of new design features (such as those that may affect the design rules). Moreover, once you have gained sufficient experience in this field, many other functions can be achieved.
For example, if you can write your own DRC, you can write your own bill of materials (BOM) creation tool, so that you can better handle specific user needs, such as how to obtain the "extra hardware" of devices that are not part of the circuit diagram database (such as Socket, heat sink or screwdriver). Or designers can write their own Verilog netlist analyzer, which has sufficient flexibility in the design environment, such as how to obtain Verilog models or time files suitable for specific devices. In fact, since DRC traverses the entire design circuit diagram, all valid information can be collected to output the simulation and/or BOM required for the Verilog netlist analysis of the PCB design.
It is a bit far-fetched to discuss these topics without providing any program code. For this reason, we will take a circuit diagram acquisition tool as an example. This article uses the ViewDraw tool developed by Mentor Graphics, which is attached to the PADS-Designer product line. In addition, we also adopted the ViewBase tool, which is a simplified C routine library that can be called and accessed and operated on the ViewDraw database. Using the ViewBase tool, designers can easily use the C/C language to write a complete and efficient DRC tool for ViewDraw[2][3]. It should be noted that the basic principles discussed here are equally applicable to any other PCB circuit diagram tools.
Input file
In addition to the circuit diagram database, DRC also needs some input files that can describe specific situations, such as automatically connecting to the power plane with a legal power network name. For example, if the power network is named POWER, then the power plane will be automatically connected to the power plane using a back-end packaging device (if applicable to ViewDrawpcbfwd). The following is a list of input files, these files must be placed in a fixed global location, so that DRC can automatically find and read, and then save the information in the DRC at runtime.
*The file legal_pwr_net_name is optional. This file contains all the legal network names of the POWER signal, such as VCC, V3_3P and VDD. In the PCB layout/routing tool, the case of names needs to be distinguished. Generally, VCC is not the same as Vcc or vcc. VCC can be a 5.0V power supply, and V3_3P can be a 3.3V power supply. *The file legal_pwr_net_name is optional, because the back-end packaged device configuration file usually must contain a set of legal power cord network names. If you use the Allegro wiring tool from Cadence Design Systems, the pcbfwd file name is allegro.cfg and has the following entry parameters:
Grounding: VSS CGND GND GROUND
Power supply: VCC VDD VEE V3_3P V2_5P 5V 12V
If DRC can directly read the allegro.cfg file instead of legal_pwr_net_name, then better results will be obtained (that is, the probability of introducing errors is smaller).
Some symbols must have external power cord pins because these symbols are not connected to the regular power cord layer. For example, the VCC pin of an ECL device is either connected to VCC or to the GROUND; its VEE pin can be connected to the GROUND or -5.0V plane. In addition, the power line pins can also be connected to the filter before reaching the power line layer.
The power line pin is usually not connected to the device symbol. On the contrary, an attribute of the symbol (here called SIGNAL) describes which pin is the power pin or the ground pin and describes the network name that the pin should be connected to.
SIGNAL=VCC: 10
SIGNAL=GROUND: 20
DRC can read this attribute and ensure that the network name is saved in the legal_pwr_net_name file. If the legal_pwr_net_name does not contain the network name, the power pin will not be connected to the power plane, and this problem is indeed very serious.
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