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The Design of Parallel Processing with FPGA
PCB News
The Design of Parallel Processing with FPGA

The Design of Parallel Processing with FPGA


Digital Intermediate Frequency

The so-called intermediate frequency, as its name implies, refers to a signal form of intermediate frequency. Intermediate frequency is relative to baseband and radio frequency signals. Intermediate frequency can have one or more levels, and it is the bridge between baseband and radio frequency.


As shown in Figure 1, the mid-frequency section is digitally implemented, known as digital mid-frequency. Digital IF technology usually includes up-down frequency conversion (DUC/DDC), peak factor attenuation (CFR), and digital predistortion (DPD).


DUC implements the conversion from the Baseband signal to the Passband signal. The sampling rate of the input complex baseband signal is relatively low, usually the symbol rate of digital modulation. The baseband signal is filtered and then converted to a higher sampling rate to modulate to the NCO's IF carrier frequency.

DUC usually needs to complete a Pulse shaping and then modulate the intermediate frequency carrier to drive the back analog converter via DAC.

Frequency spectrum integer of baseband signal is accomplished by Channel Filter, usually by FIR. Interpolation partially accomplishes signal sampling rate transformation and filtering, which can be achieved by CIC or FIR. For a narrowband signal, if a high sampling rate transformation is required, CIC will be very appropriate, and will be superior to FIR in terms of performance or resource savings.

NCO is a numerical control oscillator, also known as DDS, that can be used to produce a pair of orthogonal sine and cosine carrier signals that are mixed with the baseband signal after interpolation (increasing the sampling rate) to complete the spectral shift.

In contrast to DUC, DDC basically does the following:

1. Spectrum Down Move: Move the ADC's digital signal to the baseband from the mid-frequency to the useful spectrum

2. Sampling rate reduction: Reduce the frequency shift data from ADC's high sampling rate to an appropriate sampling rate level by decimaTIon.

3. Channel Filtering: Before I/Q signals are sent to the baseband for processing, they need to be filtered aFPGAin

In fact, the digital up-down conversion technology is widely applied, and it is an indispensable function in wireless communication, cable TV network (Cable Modem), digital TV broadcasting (DVB), medical imaging equipment (ultrasound), and military fields.


At present, many wireless communication systems, such as WCDMA, WiMAX, in which the frequency signal is usually composed of several independent baseband signals. The synthesized IF signal has a large Peak-to-Average RaTIo and conforms to the FPGAussian distribution. In general, the linear region of power amplifier (PA) is limited, and the working range of PA corresponding to the larger PAR's intermediate frequency signal will be reduced, resulting in a decrease in PA efficiency. Therefore, it is very important to reduce the PAR of IF signal before PA. Peak factor attenuation (CFR) is used to accomplish this function. It will help to ensure the linearity of PA output, reduce out-of-band radiation and improve PA efficiency.

Currently, CFR algorithms used in IF include peak clamping (Clip), peak trimming (Peak Windowing), and peak reduction (Peak CancellaTIon). The performance and realizability of peak trimming method are moderate. Peak reduction has better out-of-band characteristics than peak trimming, but it requires more resources of the field bus.


In wireless communication systems, PA output is often required to have high linearity to meet the stringent requirements of air interface standards, while linear amplifier is very expensive. In order to improve the output efficiency and reduce the cost of PA as much as possible, the non-linearity of PA must be corrected. Pre-distortion processing of the input signal of PA is a good choice.

DPD implementations fall into two categories: lookup table (LUT) and polynomial. The advantages and disadvantages of the two algorithms are shown in Table 1.

Design of Digital Intermediate Frequency Based on Parallel Processing of FPGA

Advantages of implementing on FPGA

Implementation of Digital Intermediate Frequency by FPGA

With the maturity of broadband wireless communication technology such as WiMAX/LTE, the requirement for digital intermediate frequency bandwidth of wireless devices is also increasing. At the same time, multi-antenna technologies such as MIMO are being widely used, and the number of channels of digital intermediate frequency is also increasing rapidly.

For such a large bandwidth requirement, many DSP processors are difficult to meet the practical application, while the dedicated chip (ASSP) lacks the corresponding flexibility. The digital mid-frequency (IF) is implemented by using the FPGA, which can well coordinate the conflict between processing power and flexibility. At the same time, Altera has developed a large number of digital IF reference designs and IP for 3G/4G applications, which simplifies the development difficulty of designers and shortens the design cycle.

The feature of the hardware is that it is suitable for data path implementation with high speed and uncomplicated logic relationship.

Through our analysis of previous DDC and DUC functions, we find that the main modules and operations for DDC/DUC are CIC/FIR filter, NCO, interpolation/decimation, mixing. These processes are basically simple, but computationally fast, and are very suitable for the implementation of the field programmer.

On the other hand, the advantage of a parallel architecture over a DSP processor is that of a FPGA. Once a DDC/DUC module is completed, it can be extended to multiple DDC/DUC with simple replication. At the same time, an ADC/DAC device can connect multiple channels of DC/DUC, which makes it easy to support multi-carrier (MulTI-carrier) systems.

However, sometimes the internal resources of the field bus are limited. Multiplex DDC/DUC can even do time-division multiplexing, and share a DDC/DUC circuit. Of course, the working clock of the circuit needs to be increased by a multiple, as long as the performance of the field bus is within the allowable range. Altera has reference designs that support including WCDM A, TD-SCDMA, and WiMAX.

CFR circuits are computationally intensive, such as TD-SCDMA, with sampling rates ranging from 61.44MHz to 92.16MHz. Parallel processing based on FPGA can be easily completed.

The polynomial DPD is divided into forward and reverse modules. The forward module is a predistorter and consists of multiple FIR filters. It is very suitable for the hardware implementation on the FPGA. The IP core of Altera can provide perfect FIR support. Reverse modules provide reference designs for specific convergence algorithms, such as LMS, RLS, and Altera. For RLS, the reference design of Altera uses QR decomposition, which shortens the convergence time and improves the stability of the algorithm.

Resources provided by Altera

Altera has done a lot in IP core, control glue logic, interface logic, design tools and processes, as well as reference design, in addition to taking into account the actual situation of digital IF applications in device design.

Altera's Cyclone and Stratix series have greatly improved both in number and speed in terms of embedded memory and multiply and add modules on the resources of the devices in the field of the field programmable FPGAte.

In the aspect of IP core components of DSP, Altera can provide functions such as FIR, NCO, CIC, CORDIC, etc. For user-friendly system integration, there is also a unified interface for interconnecting these modules: the Avalon Streaming (Avalon-ST) interface. In addition, for multichannel reuse and demultiplexing, Altera has designed a Packet Format Converter for the Avalon-ST interface, which provides time and space interfaces between single or multiple Avalon-ST channels in input and single or multiple Avalon-ST channels in output for multichannel reuse and demultiplexing.

In some areas that require flexibility, such as DPD, Altera's Nos II embedded processor just works. For example, on DPD's feedback path, it can help users increase their own interpolation routines flexibly. The Nios II embedded processor can also help the system do some data statistics, parameter reassignment, and other management work.

In the design of verification tools and processes, Altera pushes forward the integrated design process of MATLAB/Simulink+DSP Builder+Quartus II. As shown in Figure 3.

Simulink can also integrate ModelSim and the embedded logic analyzer SignalTap-II on the FPGA to assist users in functional simulation and debugging. In addition, hardware in Loop (Hardware In Loop) functionality can help users validate the design algorithm on the actual hardware, while also accelerating the validation speed.

Reference Design


Altera's WiMAX DDC/DUC reference design is based on 1024-point FFT OFDM with a working bandwidth of 10 MHz. The sampling rate of the baseband signal is 11.424 MSps, or Symbol Rate. The sampling rate of IF signal is 91.392 MSps. From baseband to mid-frequency, a total of eight times the sampling rate variation is required.

As we mentioned earlier, CIC is suitable for narrow-band high-power transformations where only 8-fold transformations are required and the useful signal bandwidth is 10MHz, so FIR is a better choice for decimation or interpolation filtering.

When dividing functions, we consider the resources and efficiency of the implementation, dividing the reshaping filter and decimation interpolation filter into three FIRs to design: G(z) is responsible for spectral reshaping, usually root-rising cosine (RRC) filter; Q(z) is responsible for double decimation or interpolation filtering; P(z) is responsible for quadruple decimation or interpolation filtering.

In order to save the resources of the field bus and improve the performance, the G(z) of the working frequency is designed as 111-order FIR with narrow transition band. Q(z) second, order 79; P(z) has only 39 order and its operating frequency. The combined response of the three filters, shown in Figure 5, fully meets the template (Mask) required by WiMAX.

In the specific implementation of the field bus, we consider that the filter characteristics of I/Q are identical. In order to save device resources, we multiplex the three-stage FIR of I/Q. See Figure 6.

On DDC, we first mix the 91.392 MSps IF signal with NCO through Oversample to 182.784 MSps in two consecutive clock cycles, and then through three-stage FIR, we get two I/Q signals of 11.424 MSps.

On DUC, FIR works at 22.848 MSps, 45.696 MSps and 182.784 MSps, respectively. By adding the two IQ signals of mixing frequency, a band pass real number signal is obtained with a sampling rate of 91.392 MSps.

On multichannel reuse/demultiplexing, we use Altera's Valon-ST Package Format Conversion Module (PFC) for module interconnection.

A typical requirement in a WiMAX base station is two send antennas and four receive antennas, and this reference design can also support two send antennas and four receive antennas.

The relative constellation error (Relative Constellation Error) of DUC is much better than the specified value through simulation validation of the reference design. For example, at 64QAM 3/4 rate, the measured RCE is -55.29dB. The acceptance sensitivity and Adjacent Channel Rejection indices of DDC are much better than expected.


WiMAX system has higher requirements for CFR. Due to the 64QAM modulation, the Error Vector Amplitude (EVM) requires 3%, which also has stricter requirements for Peak-to-Average Ratio (PAR) and Neighbor Channel Leakage Ratio (ACLR). Altera's WiMAX CFR scheme uses the Constrained Clipping algorithm of the Georgia Institute of Science and Technology, which has EVM 3%, PAR Reduction 5dB and very small out-of-band spread.

Design of Digital Intermediate Frequency Based on Parallel Processing of FPGA

Design of Digital Intermediate Frequency Based on Parallel Processing of FPGA


The mid-frequency bandwidth of WiMAX is more than 10MHz, and adaptive algorithms such as LMS/RLS need to be introduced, which requires a high degree of DSP processing capability and flexibility for the entire DPD module. The design requirements can be well met by using Altera's "in-chip processor NIOS II+FPGA hardware co-processing unit".

Design of Digital Intermediate Frequency Based on Parallel Processing of FPGA

As shown in Figure 8, the forward module is a predistorter and consists of multiple FIR filters. In the reverse link, we collect a set of 64 samples in the Sample Cache. In, the Nios embedded processor can help calculate the input of CORDIC, and the CORDIC accelerator performs QR decomposition. Nios then performs a reverse conversion to update the coefficients of FIR filters in the forward link. Using the soft processor NIOS+CORDIC accelerator to complete the upper triangle matrix operation of QRD_RLS is flexible, and we can adjust the number of CORDIC accelerators to increase the inverse. Data throughput to the module.