PCB Blog - The main points of designing PCB board with fpga pcb design

As field programmable gate arrays (FPGAs) have evolved into truly programmable system-on-chips, the task of designing printed circuit boardswith these chips has become more complex. Current circuit densities of millions of gates and transceiver data rates of more than 6 Gbps and other considerations impact the mechanical and electrical board-level design efforts of system developers. Die, chip package and circuit board form a tightly connected system, in this system, to fully realize the function of FPGA, the PCB board needs to be carefully designed. When designing with high-speed FPGAs, it is crucial to consider several design issues before and during board development. These include: reducing system noise by filtering and distributing sufficient power evenly across all devices on the PCB; properly terminating signal lines to minimize reflections; minimizing crosstalk between traces on the board; reducing Effects of ground bounce and Vcc reduction (also known as Vcc sag); correctly matching impedance on high-speed signal lines. Anyone designing an IC package for a very high-performance FPGA must pay special attention to the balance between signal integrity and versatility for all users and applications. For example, Altera's Stratix II GX devices in a 1,508-pin package operate down to 1.2V and feature 734 standard I/Os and 71 low-voltage differential signaling (LVDS) channels. It also has 20 high-speed transceivers that support data rates up to 6.375Gbps. This enables the architecture to support many high-speed networking and communication bus standards, including PCI Express and SerialLite II.

In PCB board design, users can reduce crosstalk by optimizing the pinout. Signal pins should be placed as close as possible to ground pins to reduce loop lengths within the package, especially for critical high-speed I/O. In high-speed systems, the dominant source of crosstalk is inductive coupling between signal paths within the package. When the output transitions, the signal must find a return path through the power/ground plane. Current changes in the loop create magnetic fields that cause noise on other I/O pins near the loop. This situation is exacerbated when the outputs are converted at the same time. Because the smaller the circle, the smaller the inductance, so packages with power or ground pins close to each high-speed signal pin can minimize the effects of crosstalk on nearby I/O pins. To reduce the cost of the board and improve the system signal integrity of all signal paths,careful design and construction of the board material, number of layers (stacking) and layout are required. Sending hundreds of signals from the FPGA to or around the board is a difficult task requiring the use of EDA tools to optimize pinout and chip placement. Sometimes a slightly larger FPGA package can reduce board cost because it reduces the number of layers on the board and other board processing constraints.

A high-speed signal path on PCB board, represented by a board trace that is very sensitive to interruptions, such as vias between board layers and board connectors. These and other interruptions reduce the edge rate of the signal, causing reflections. Therefore, designers should avoid vias and via stubs. If vias are unavoidable, keep the via leads as short as possible. When routing differential signals, use a via of the same structure for each path of the differential pair; this leaves the signal interruption caused by the via in common mode. If possible, use blind vias over regular vias,or use back-drilling as there will be less interruption due to loss of via root.

To improve the signal integrity of the clock signal, the following guidelines should be followed: Keep the clock signal on a single board layer as much as possible before it is sent to the board components; always use a plane as the reference plane. Send fast edge signals along inner layers adjacent to the ground plane to control impedance and reduce EMI. Terminate the clock signal properly to minimize reflections. Use point-to-point clock traces.

Some FPGAs, such as the Stratix II GX family, have on-chip series termination resistors that support several I/O standards. These on-chip resistors can be set as 25 ohm or 50 ohm single-ended resistors and support LVTTL, LVCMOS, and SSTL-18 or SSTL-2 single-ended I/O standards; in addition, 100 ohm LVDS and HyperTransport inputs are supported on-chip differential matching resistors. The differential transceiver I/Os have on-chip resistors programmable to 100, 120 or 150 ohms and are auto-calibrated and reflective. Using internal resistors instead of external devices has several benefits to the system. On-chip termination improves signal integrity by eliminating lead effects and enabling reflections on transmission lines. On-chip termination also minimizes the number of external components required, allowing designers to use fewer resistors, fewer board traces, and less board space. In this way, the layout can be simplified, the design cycle can be shortened, and the system cost can be reduced. Board reliability is also enhanced due to fewer components on the board. In board design, there are several guidelines for routing microstrip and stripline to minimize crosstalk. For the double-strip line layout, the wiring is carried out on the two-layer inner board, and there is a voltage reference surface on both sides. At this time, all the wires of the adjacent layer boards use the orthogonal wiring technology to maximize the medium between the two signal layers. Material thickness, and normalize the distance between each signal layer and its adjacent reference plane, while maintaining the required impedance.

Microstrip or stripline routing guidelines with trace spacing at least three times the thickness of the dielectric layer between the board routing layers; use simulation tools to pre-simulate its behavior. Use differential instead of single-ended topology for critical high-speed networks to minimize the effects of common-mode noise. Within design limits, try to match the positive and negative pins of the differential signal path. To reduce the coupling effect of single-ended signals, leave appropriate spacing (greater than three times the trace width), or route on different board layers (adjacent layer routing is orthogonal to each other). Also, using a simulation tool is a good way to meet spacing requirements. Minimize parallel lengths between signal terminations.

Simultaneous transition noise,clock and I/O data rates increase with a corresponding reduction in the number of output transitions and a concomitant increase in transient currents during signal path discharge and charging.These currents can cause board-level ground bounce, a momentary rise/fall of ground voltage/Vcc. Large transient currents from non-ideal power supplies can cause a momentary drop in Vcc (Vcc dip or dip). Several good board design rules are given below to help reduce the effects of these simultaneous transition noises. Configure unused I/O pins as outputs and drive them low to reduce ground bounce.Minimize the number of simultaneous transition output pins and distribute them evenly throughout the FPGA I/O section. When a high edge rate is not required, use a low slew rate at the FPGA output.Place Vcc between the ground planes of the multilayer board to eliminate the effects of high-speed traces on each layer. Dedicating all board layers to Vcc and ground makes these planes resistive and inductive, providing a low inductance source with lower capacitance and noise, and returning logic signals on signal layers adjacent to these planes.

Pre emphasis, equalization fpga pcb design

The high-speed transceiver capabilities of FPGAs make them efficient programmable system-on-a-chip components, but they also present unique challenges for board designers. A key issue, especially related to layout, is the frequency-dependent transmission loss,mainly caused by the skin effect and dielectric losses. When high-frequency signals are transmitted on conductor surfaces (such as PCB board traces), the skin effect occurs due to the self inductance of the wires. This effect reduces the effective conduction area of the wire, attenuating the high frequency components of the signal. Dielectric losses are caused by the capacitive effect of the dielectric material between the layers.Skin effect is proportional to the square root of frequency, while dielectric loss is proportional to frequency; therefore, dielectric loss is the dominant loss mechanism for high-frequency signal attenuation.The higher the data rate, the more severe the skin effect and dielectric loss. The reduction in signal level on the link is acceptable for a 1Gbps system, but unacceptable for a 6Gbps system.

However, today's transceivers feature transmitter pre-emphasis and receiver equalization to compensate for high-frequency channel distortion.They also enhance signal integrity and ease trace length constraints. These signal conditioning techniques extend the life of standard FR-4 materials and support higher data rates. Due to signal attenuation in FR-4 material, the allowable trace length is limited to a few inches when operating at 6.375Gbps. And pre-emphasis and equalization can extend it to more than 40 inches. Programmable pre-emphasis and equalization are integrated into some high-performance FPGAs, such as Stratix II GX devices, which allow the use of FR-4 materials and relax layout constraints such as trace lengths, reducing board costs. The pre-emphasis function can effectively boost the high frequency components of the signal. The 4-tap pre-emphasis circuit in Stratix II GX reduces signal component scatter (spatial spread from one bit to another). The pre-emphasis circuit provides 500% pre-emphasis, and each tap can be optimized to 16 levels depending on data rate, trace length and link characteristics. In addition to the input gain stage, the device allows the board designer to have an equalization level of 17dB, using any of the 16 equalizer stages to overcome board losses. Equalization and pre-emphasis can be used in concert environments or to optimize specific links individually. Designers can change the pre-emphasis and equalization levels in Stratix II GX FPGAs while the system is running, or during card configuration after it has been inserted into a backplane or other chassis. This gives the system designer the flexibility to automatically set the pre-emphasis and equalization levels to predetermined values. Alternatively, these values can be dynamically determined based on which slot the board is plugged into the chassis or backplane.

EMI issues and debugging
EMI caused by a printed circuit board is directly proportional to the change in current or voltage over time, and the series inductance of the circuit. Efficient board design has the potential to minimize EMI, but not necessarily eliminate it completely. Eliminating "intruder" or "hot" signals, and sending signals with proper reference to the ground plane, also helps reduce EMI, the use of surface mount components that are common in today's market is also a way to reduce EMI. It has become increasingly difficult to debug and test complex high-speed PCB board designs because some traditional board debug methods, such as test probes and "Bed-of-nails" testers, may not work for these designs. This new high-speed design can take advantage of JTAG test tools with in-system programming and built-in self-test capabilities that FPGAs may have. Designers should use the same guidelines to set the JTAG test clock input (TCK) signal as the system clock. In addition, it is important to keep the JTAG scan chain trace length between the test data output of one device and the test data input of another device to a minimum. 

Designing successfully with embedded high-speed FPGAs requires extensive high-speed board design practice, as well as a solid understanding of FPGA capabilities such as pinout, board materials and stacking, board layout, and termination modes. Proper use of pre-emphasis and equalization of the built-in transceiver is also important. The above points combine to achieve a reliable design with stable manufacturability. Careful consideration of all of these factors, combined with proper simulation and analysis, can reduce the likelihood of surprises in PCB board prototypes and will help reduce the stress of board development projects.