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PCB board layout design review elements
PCB Blog
PCB board layout design review elements

PCB board layout design review elements

2022-04-22
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Author:pcb

一、DFM Requirements for Layout

1. The preferred process route has been determined, and all devices have been placed on the PCB board.

2. The origin of the coordinates is the intersection of the left and lower extension lines of the board frame, or the lower left pad of the lower left socket.

PCB board

3. The actual size of the PCB, the location of the positioning device, etc. are consistent with the process structure element diagram, and the device layout in the area with limited device height requirements meets the requirements of the structure element diagram.

4. The position of the dial switch, reset device, indicator light, etc. is appropriate, and the handle bar does not interfere with the surrounding devices.

5. The smooth radian of the outer frame of the board is 197mil, or it can be designed according to the structural dimension drawing.

6. The ordinary board has a 200mil process edge; the left and right sides of the back plate have a process edge larger than 400mil, and the upper and lower sides have a process edge larger than 680mil. The device placement does not conflict with the window opening position.

7. All kinds of additional holes to be added (ICT positioning hole 125mil, handle strip hole, elliptical hole and fiber support hole) are missing and set correctly.

8. The device pin spacing, device orientation, device spacing, device library, etc. processed by wave soldering take into account the requirements of wave soldering processing.

9. The device layout spacing meets the assembly requirements: the surface mount device is greater than 20mil, the IC is greater than 80mil, and the BGA is greater than 200mil.

10. The crimping element has a surface distance of more than 120 mils above it, and there is no device in the through area of the crimping element on the soldering surface.

11. There are no short devices between tall devices, and no SMD devices and short and small plug-in devices are placed within 5mm between devices with a height greater than 10mm.

12. Polarity devices are marked with polar silkscreen. The X and Y directions of the same type of polarized plug-in components are the same.

13. All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14. There are 3 positioning cursors on the surface containing the SMD device, which are placed in an "L" shape. The distance between the center of the positioning cursor and the edge of the board is greater than 240mil.

15. If you need to do panel processing, the layout is considered to be easy to make up, which is convenient for PCB processing and assembly.

16. The edge of the board with the gap (special-shaped edge) should be filled by the method of milling groove and stamp hole. The stamp hole is a non-metallized hole, generally 40 mil in diameter and 16 mil from the edge.

17. The test points for debugging have been added in the schematic diagram, and the positions in the layout are appropriate.

Layout thermal design requirements

18. The heating element and the exposed device in the shell are not close to the wire and the thermal element, and other devices should also be properly kept away.

19. Considering the convection problem in the placement of the radiator, there is no high device interference in the projection area of the radiator, and the range is marked on the mounting surface with silk screen.

20. The layout takes into account the reasonable and smooth cooling channels.

21. Electrolytic capacitors should be properly separated from high-heat devices.

22. Consider the heat dissipation of high-power devices and devices under the gusset.

二、Layout Signal Integrity Requirements

23. The origin matching is close to the transmitting device, and the termination matching is close to the receiving device.

24. Place decoupling capacitors close to related devices

25. Crystals, crystal oscillators and clock driver chips are placed close to related devices.

26. High-speed and low-speed, digital and analog are divided into modules.

27. Determine the topology of the bus according to the analysis and simulation results or existing experience to ensure that the system requirements are met.

28. If the board design is to be modified, simulate the signal integrity problems reflected in the test and give solutions.

29. The layout of the synchronous clock bus system meets the timing requirements.

EMC requirements

30. Inductive devices that are prone to magnetic field coupling such as inductors, relays and transformers are not placed close to each other. When there are multiple inductor coils, the direction is vertical and there is no coupling.

31. In order to avoid electromagnetic interference between the devices on the soldering surface of the veneer and the adjacent veneers, no sensitive devices and strong radiation devices are placed on the soldering surface of the veneer.

32. The interface device is placed close to the edge of the board, and appropriate EMC protection measures (such as shielding case, hollowing out the power supply ground, etc.) have been taken to improve the EMC capability of the design.

33. The protection circuit is placed near the interface circuit, following the principle of protection first and filtering later.

34. Devices with high transmit power or particularly sensitive devices (such as crystal oscillators, crystals, etc.) are more than 500 mils away from the shield and shield shell.

35. A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong devices and signals.

Layer Setup and Power Ground Splitting Requirements

36. Vertical routing rules must be defined when two signal layers are directly adjacent.

37. The main power supply layer should be adjacent to its corresponding ground layer as much as possible, and the power supply layer should meet the 20H rule.

38. Each routing layer has a complete reference plane.

39. The multi-layer board is stacked and the core material (CORE) is symmetrical to prevent the uneven density distribution of the copper skin and the asymmetric thickness of the medium from warping.

40. The thickness of the board should not exceed 4.5mm. For the board thickness greater than 2.5mm (the backplane is greater than 3mm), the technicians should confirm that there is no problem in PCB processing, assembly and equipment. The thickness of the PC card board is 1.6mm.

41. When the aspect ratio of the via is greater than 10:1, it should be confirmed by the PCB manufacturer.

42. The power supply and ground of the optical module are separated from other power supplies and grounds to reduce interference.

43. The power supply and ground processing of key devices meet the requirements.

44. When there are impedance control requirements, the layer setting parameters meet the requirements.

Power Module Requirements

45. The layout of the power supply part ensures that the input and output lines are smooth and do not cross.

46. When the single board supplies power to the pinch board, the corresponding filter circuit has been placed near the power outlet of the single board and the power inlet of the pinch board.

三、Other Requirements

47. The layout takes into account the smoothness of the overall wiring, and the main data flow is reasonable.

48. According to the layout results, adjust the pin assignments of devices such as resistor exclusion, FPGA, EPLD, bus driver, etc. to make wiring.

49. The layout takes into account the appropriate increase in the space of dense traces to avoid the situation that cannot be routed.

50. If special materials, special devices (such as 0.5mmBGA, etc.), and special processes are adopted, the delivery period and machinability have been fully considered, and they have been confirmed by PCB manufacturers and craftsmen.

51. The pin-to-pin correspondence of the gusset connector has been confirmed to prevent the direction and orientation of the gusset connector from being reversed.

52. If there are ICT test requirements, the feasibility of adding ICT test points should be considered during layout, so as to avoid difficulty in adding test points during the wiring phase.

53. When high-speed optical modules are included, the layout should give priority to the optical port transceiver circuit.

54. After the layout is completed, a 1:1 assembly drawing is provided for the project person to check whether the device package selection is correct against the device entity.

55. The inner plane has been considered to be indented at the window opening, and an appropriate prohibited wiring area has been set up on PCB board.