PCB Blog - Design of hardware circuit of PCB board testing machine based on FPGA

In order to improve the testing speed of the PCB board testing machine, simplify the design of the circuit board, improve the reconfigurability of the system and the convenience of testing algorithm transplantation, a hardware control system design scheme of the PCB board testing machine based on FPGA is proposed. In the design, the field programmable gate array (FPGA) EP1K50 of Altera Corporation is selected, and the hardware design and debugging of the control system are completed by using the EDA design tools Synplify, Modelsim, Quartus II, and Verilog hardware description language, and the problem that is difficult to realize by conventional circuits is solved. . The basic test principle of the PCB board light test machine is Ohm's law. The test method is to add a certain test voltage between the points to be tested, use the decoding circuit to select the two points to be tested on the PCB board, and obtain the corresponding resistance value between the two points. The voltage signal, through the voltage comparison circuit, tests the resistance or continuity between the two points. Repeat the above steps several times to test the entire circuit board. Due to a large number of tested points, the general test machine is more than 2048 points, and the test control circuit is more complicated. The search method and switching method of the test point directly affect the test speed of the test machine. This paper studies the design of the hardware control system based on FPGA.

Hardware control system

The test process is to control the test circuit to turn on different test switches under the control of the host computer. The test machine system is composed of the following parts: the upper computer PC104, the test control logic (implemented by FPGA), and the high voltage test circuit. Among them, the upper computer mainly completes the functions of human-computer interaction, test algorithm, test data processing, and control output. The FPGA controls the high-voltage test circuit to complete the test process of the PCB board. This system uses a PC104 as the upper computer and FPGA as the control of the test by the upper computer through the PC104 bus.

Interface circuit between FPGA and PC104

PC104 bus is an industrial control bus specially defined for embedded control, and its signal definition is basically the same as that of the ISA bus. PC104 bus has 4 types of bus cycles, namely 8-bit bus cycle, 16-bit bus cycle, DMA bus cycle and refresh bus cycle. The 16-bit I/O bus cycle is 3 clock cycles, and the 8-bit I/O bus cycle is 6 clock cycles. In order to improve the speed of communication, the ISA bus adopts a 16-bit communication mode, namely the 16-bit I/O mode. In order to make full use of the resources of PC104, the FPGA is configured online after the expansion of the system bus of PC104. During normal operation, it communicates with FPGA through the PC104 bus.

The interface between FPGA and Serial A/D and D/A Devices

According to the system design requirements of the tester, it is necessary to perform a self-check on the test voltage and the two-channel reference voltage, that is, there are at least three A/D conversion channels. The reference voltage of the two comparison circuits is output by the D/A, so the D/A channel of the system requires two channels. In order to reduce the number of control signal lines of A/D and D/A, serial A/D and D/A devices are selected. Comprehensive performance, price, and other factors, the selected A/D device is TLC2543, and the D/A device is TLV5618. The TLV5618 is a dual 12-bit voltage output DAC with a buffered reference input (high impedance) from TI, which is digitally controlled via a CMOS-compatible 3-wire serial bus. The device accepts a 16-bit command word and generates two D/A analog outputs. TLV5618 only has a single I/O cycle, which is determined by the external clock SCL K, which lasts for 16 clock cycles, writes the command word into the on-chip register, and performs D/A conversion after completion. TLV5618 read-in command word is valid from the falling edge of CS and starts to read data from the falling edge of the next SCLK. After reading 16-bit data, it enters the conversion cycle until the next falling edge of CS occurs. The TLC2543 is a 12-bit, switched capacitor successive approximation A/D converter with serial control and 11 inputs from TI. On-chip converters feature high speed, high precision, and low noise. The working process of TLC2543 is divided into two cycles: the I/O cycle and the conversion cycle. The I/O cycle is determined by the external clock SCLK, which lasts for 8, 12, or 16 clock cycles, and performs two operations at the same time: input 8-bit data to the on-chip register in MSB mode on the rising edge of SCLK; output in MSB mode on the falling edge of SCLK 8, 12, 16-bit conversion result. The conversion cycle begins on a falling edge of SCLK in the I/O cycle until the EOC signal goes high, indicating that the conversion is complete. In order to be consistent with the I/O cycle of TLV5618, the MSB method is adopted, and the timing of the 16-clock transmission of CS is used.

Since both devices are SPI interfaces, they can be connected to the same SPI bus and operate on different devices through different chip select signals. Because the SPI interface protocol is complex, and as can be seen from Figure 3, the timing of these two devices does not use all the SPI interface timing. In order to realize the timing in line with the above logic and reduce the waste of standard SPI interface IP checking FPGA resources, the design adopts Verilog hardware description language to realize the design method of the synchronous state machine (FSM), and writes ADC and DAC to control the timing sequence. The program is actually a nested state machine, and the master state machine and the slave state machine constitute finite state machines with different functions under different input signal conditions through the bus started by the control line. It can be known from FIG. 3 that the D/A operation has 4 states, and the A/D operation has 7 states. Several states in the two states are the same, so a finite state machine can be used to complete the operation of the serial A/D and D/A. The program is actually a nested state machine. The master state machine and the slave state machine form a more complex finite state machine with different functions under different input signals through the bus started by the control bus. Drive clock (SCLK) and data bus (SI, SO) are shared by A/D and D/A operations. Since the write cycle of the operation has 16 clock cycles and the read cycle has 12 clock cycles, the module is done in three nested finite state machines. In the system design, the AD and DA operations are encapsulated into a single module, and the upper-layer control module outputs the command word and control signal to start the corresponding operation of this module. After the operation is completed (enters the idle state), this module sends the corresponding status signal to the upper-layer module.

FPGA programming framework

The FPGA on-chip program is the key to the correct operation of the entire test system. According to the top-down FPGA design principle, the system is divided into 5 independent modules, namely the communication module (ISA), test module (TEST), AD/DA module, decoding module (DECODER), and RAM control module (RAMCTL). ISA module: system communication and control module, completes communication with the host computer, command word interpretation, control signal generation, etc. The system starts the ADDA module to complete the output of the reference voltage according to the on-resistance, insulation voltage, and other parameters transmitted by the host computer; starts the test module to complete the test process according to the test command. Data is transferred between multiple synchronous state machines running synchronously, and it is more difficult to control the data communication and data synchronization between multiple processes. RAM control module: Before the test starts, the host computer transmits the information of the test point to the ISA module through the bus, and the ISA module stores it in the on-chip RAM; after the test is completed, the test result in the RAM is transmitted to the host computer. During the test, the test module opens the corresponding test switch by reading the information of the test point in the RAM and then saves the test result in the RAM. In this way, both modules require to read and write RAM to achieve data sharing between the two modules, which requires a control signal to connect the two groups of reading and write signal lines to the RAM module respectively, and the RAM control module completes this function. Test module (TEST): Although there are various test procedures, such as switch card self-check, continuity test, insulation test, etc., the test procedure is the same, namely test scan. The working process of the test is: add the reference voltage of the comparison circuit → turn on the switch of the point to be tested → delay → read the comparator result → test another set of test points. This module enters different test processes according to different opcodes. The test result and the test point number together form 13-bit data and save it in RAM, and cover the number information of the original test point.

Decoding module (DECODER): This module hangs after the test module (TEST), it completes the mapping of switch numbers to actual circuits. Due to the different forms of the test pin array and the different hardware designs of the decoding circuit and the control circuit, the test switch information output by the upper-level module cannot be directly used as an output to control the test switch circuit. The decoding module completes the conversion between the two. AD/DA module (AD/DA): Design the SPI bus interface to operate the A/D and D/A devices, the module is started with the allowable (adorable, damnable) signal and the busy signal is used as the conversion completion flag signal. D/A operations are encapsulated relative to other modules. Each module of the system is written in Verilog hardware description language, and multiple layers of nested synchronous state machines (FSM) are used to complete the logic function of the whole system; each module uses the simulation tool Modelsim to complete the function simulation of the module, and the system completes the function test Use Altera's integrated routing tool QuartusII to complete post-system simulation and synthesis, wiring, and make full use of the IP core provided by Altera to optimize the program modules; the top-level design adopts the block diagram input method, and the data flow between modules is more intuitively represented by the block diagram. . The hardware control system of the PCB board testing machine based on FPGA improves the testing speed of the PCB board testing machine and simplifies the circuit design. In addition, due to the reconfigurable characteristics of FPGA, it has laid a good foundation for the further optimization and upgrading of the software algorithm and hardware structure of the system and has a good application prospect on PCB board.