2022-07-20

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Author：pcb

As the computer industry moves towards DC-DC converters capable of delivering up to 200A at 1V, **PCB board** layout techniques need to meet the requirements of this challenging emerging converter. To compare the effects of various wiring defects, we focus on the effects of parasitic inductances in the circuit, especially those associated with the source, drain, and gate of switching MOSFETs. We built a PCB board for testing a DC-DC converter that takes in 12V DC and converts it to 1.3V and outputs up to 20A. We use a plug-in board for assembly and can change the inductance at each MOSFET electrode individually or simultaneously at any time. We chose to use the inductance value as a percentage of the overall inductance of a specially designed 2-inch board, rather than an actual value because the wiring person only knows the length of a particular trace and not necessarily the value of its inductance.

Test design

We use converter efficiency to measure the effectiveness of these parasitic inductances. This is because efficiency is a standard measure of DC-DC converter performance. The test is divided into the following parts: adjust the proportional coefficient of each inductance value of the MOSFET drain, source, and gate, and observe the effect on the synchronous rectifier by measuring the conversion efficiency. Through the combination of any two of the above, to understand the relationship between them. The inductance test board has an inductance of 43nH and is typically set to 0%, 25%, 50%, and 100%. In our experiments, the parasitic resistance on the inductance test board has little effect and can be ignored. Since the deleterious effects of parasitic inductances are frequency dependent, we experimented at three preset switching frequencies: 300kHz, 600kHz, and 1MHz. This allows us to see how important it will be for the design to move from normal switching frequencies to higher frequencies in the future. We all know that in power circuits, the length of all traces must be kept short to avoid voltage and current ringing, reduce the overall EMI of the board, and avoid negatively affecting the "more stable" components in the circuit (especially for analog control circuits and related components). In addition, the reference material shows that the source inductance of the control MOSFET has a non-linear effect on the increase of the source current fall time, resulting in higher power dissipation and lower conversion efficiency. In addition to the above phenomena, the source inductance can also cause ringing at the switch node.

Test circuits and circuit boards

The circuit used is a synchronous rectification topology operating in an open loop. This is to rule out any impact the control loop might have on circuit performance and allow us to focus on the power conversion efficiency, especially the MOSFET performance. We know that high inductance conditions can cause severe ringing, especially at the switch node. Select gate driver ICs that can tolerate this ringing without adverse effects. This four-layer circuit board uses two ounces of copper material, and the inner two layers are ground and power planes. All rules of good wiring should be observed when wiring.

Effect of gate inductance

The gate inductance has little effect on the efficiency at a switching frequency of 300kHz. At a switching frequency of 600kHz, the effect of gate inductance is much more pronounced, with a 1.2% change in efficiency at 20A. At 1MHz, the degradation in efficiency almost completely disappears. We have not investigated this reason and can guess that there is a 50% probability that the resonance factor will offset its loss. The resonance phenomenon of the MOSFET gate drive should be further investigated. We observe that the gate inductance has little effect on the efficiency of the control and synchronous MOSFETs.

Effect of source inductance

The source inductance has a more pronounced effect on efficiency. In some cases, we had to abort the test before reaching the current because the temperature of the MOSFET was greater than 130°C. Figure 5 shows the results of the control MOSFET study. A closer inspection of these results shows that at a frequency of 300kHz and an inductance of 100%, the DC-DC converter cannot operate at full 20A because the temperature of the MOSFET exceeds 130°C. The same can be found at 50% inductance, 600kHz, and 1MHz. Efficiency degradation due to source inductance is observed to be more severe than without source inductance. When the inductance is 50% and the current is 15A, the efficiency is reduced by 7% even at the switching frequency of 300 kHz. When the inductance is 100%, the efficiency deteriorates to 11%. At switching frequencies of 600kHz and 1MHz, the effect is more pronounced and the efficiency degradation is more severe than without the source inductance. Clearly, even a low source inductance reduces efficiency, especially for switching frequencies ≥ 600kHz.

Effect of Drain Inductance

Drain inductance can cause severe ringing that may be enough to cause the MOSFET to break down under extreme conditions (Figure 3). It also adversely affects efficiency. Efficiency is a function of load current and drains inductance at different frequencies. In addition, the following results can be observed: when the current is 15A, at 300kHz and 50% inductance, we have to abort the test because the temperature of the MOSFET exceeds 130℃. At the same frequency, 100% inductance, we couldn't get any readings because the ringing was too severe. At 300kHz, 12A, 50% of the drain inductance is 7% less efficient than 0%. Due to the high temperature of the MOSFET, the test cannot be performed above 15A. At 600kHz, 12.5A, 50% of the drain inductance is 8.5% less efficient than 0%. Since the MOSFET temperature is too high, the test cannot be performed above 12.5A. At 1MHz, the test cannot be performed above 5A due to the high temperature of the MOSFET.

Effect of gate-source inductance

A larger source inductance will significantly reduce the efficiency. A fundamental dependence of efficiency on gate inductance has been shown. When combined with a small source inductance, the overall picture becomes quite clear - a larger gate inductance necessarily results in a larger power loss. The interpretation of this result requires further study. We can now state that, within reasonable inductance values for the board, the drain and source inductances must be reduced to ensure high converter efficiency. The simulation yields the following results: The gate and source inductances resonate with the gate-source capacitance of the MOSFET. When the HS-FET turns off the gate source, the capacitor discharges through these inductive paths. After the MOSFET is turned off, the inductance will force the gate current to continue to flow and reverse charge the gate-source capacitance. This charge will again discharge in the same way and reverse the gate-source voltage of the HS-FET. Depending on the dip, the HS-FET can turn on again with a huge short circuit. The effect becomes severe at such high gate inductances. In some cases, even a second short-circuit effect can be seen. As part of this resonant circuit, the source inductance can also act in a second way. When a short-circuit current occurs, the source inductance limits the di/dt (rate of change of current over time) of the short-circuit current, thereby limiting losses. The source inductance also causes negative feedback to the gate-source voltage and limits short circuits. These effects especially occur where parasitic gate inductances are high. For high efficiency, this effect should be avoided by design, that is, gate inductance must be carefully designed to minimize it.

Effect of source HS - source LS inductance

We investigated the effect of the location of the parasitic source inductance on the efficiency. As a result, the control FET will have a greater effect on its efficiency than the synchronous FET in the same amount of parasitic source inductance loop. The reason for this phenomenon is that the slow switching control FET causes additional switching losses because the VDS of the control FET is higher than that of the synchronous FET (the forward voltage drop of the synchronous FET is small) during the conversion process. In addition, the feedback of parasitic inductance to the FET gate-drain voltage has a significant impact on the overall HS-FET leakage current. By comparison, the effect of parasitic source inductance on the LS-FET leakage current is only partial, since it can be bypassed by the body diode of the synchronous FET.

Effects of Parallel MOSFETs

When MOSFETs are connected in parallel, it is unlikely that each individual MOSFET loop will have the same parasitics in many cases. We have investigated the effect of additional inductance in the MOSFET drain loop on efficiency. We experimentally show the detrimental effect of parasitic inductance on the efficiency of switching MOSFETs in DC-DC converters. The conclusions are as follows: the effect of inductance in the source circuit is severe, followed by a similar inductance in the drain circuit. In our breadboard, we found no serious effects related to gate circuit inductance. The reduction in efficiency is closely related to the switching frequency of the converter. The reduction in efficiency has a lot to do with the load current. In the presence of parasitic inductances in the source and drain circuits, the greater the load current, the greater the drop in efficiency. In today's DC-DC converter applications, special care must be taken when routing the power system PCB, especially around the switching MOSFETs. One of the advantages of using a multilayer board is to reduce parasitic resistance and inductance by sinking as much current in the layers as possible. This reduces resistive losses and losses due to parasitic inductance. When designing high-frequency DC-DC converters, there are many parasitic inductance issues associated with source and drain circuits. The first is the package inductance, and it is feasible to use the recently introduced low-inductance packages for switching MOSFETs. The second item is the parasitic inductance of the PCB board, which must be controlled by using a multi-layer PCB board and reducing the trace inductance. This allows designers to use fewer capacitors for faster dynamic response and successful high-frequency designs. Parasitic inductances that cannot be avoided by design should be moved into the synchronous FET loop because the inductance in the synchronous FET has less of an effect on overall efficiency than the inductance in the control FET loop. Note: At low duty cycles, parasitic resistance in the synchronous FET loop can significantly reduce efficiency. Complex trade-offs need to be made in the design (trace width, copper thickness, effective loop range, biasing, etc.). Avoid paralleling MOSFETs. The way to replace MOSFETs in parallel is to add extra phases or use better MOSFETs. If paralleling is unavoidable, for paralleled MOSFETs, electrical symmetry must be guaranteed in the design to obtain the same current distribution and the same switching time on the **PCB board**.