PCB Tech - An analysis method of PCB power integrity using Cadence PI

Abstract: In order to solve the power integrity problem of high-speed multi-layer PCB, shorten its development cycle and improve its performance, taking the ARM11 core system as an example, a method of using CadencePI to analyze the power integrity of the PCB is proposed. By analyzing the target impedance of the power system, determine the value, quantity and layout of decoupling capacitors; analyze the DC voltage drop and current density of the power plane to improve the PCB design and optimize the power integrity of the system. Using the test platform built by the dynamic electronic load to test the PCB produced after the power simulation analysis, the system power integrity is good, indicating that the analysis results are valid.

With the speed of modern high-speed signals getting faster and faster, the signal edges are getting steeper, the power supply voltage of the chip is further reduced, and the increase in clock frequency and data reading rate requires more power consumption. Signal integrity in electronic systems At the same time of analysis and research, how to provide stable and reliable power to electronic systems has also become one of the key research directions. The analysis methods and practices of power integrity engineering are still in the stage of continuous exploration. Simulation technology is used to solve power integrity problems as much as possible in the early stage of product design under the overall plan and design criteria that meet the conditions of manufacturing and testing. It can minimize product costs and shorten the development cycle. At present, some EDA tools provide corresponding power integrity (Power Integrity, PI) simulation analysis functions. Among them, Allegro provides a good interactive working interface, and is closely integrated with its front-end products Cadence, Orcad, and Capture. The layered complex PCB design provides the most perfect solution. In this paper, the component Cadence PI in Allegro is used to analyze the power integrity of the ARM11 core system, and to test the power integrity of the PCB board to verify the results of the simulation analysis.

1 Theoretical analysis of power integrity

1.1 Concept of power distribution system

In the electronic system, the function of the power supply subsystem is to provide a stable voltage reference and sufficient drive current for all devices. Therefore, the power supply circuit and the functional circuit should have a low-impedance power connection and ground connection. An ideal power system has an impedance of 0, and the potential at any point in the plane is constant, but the actual power system has complicated parasitic capacitance and inductance, and the power supply voltage provided by the power supply chip is not an ideal constant value.

The Power Distribution System (PDS) consists of target impedance, Voltage Regulator Module (VPM), power/ground plane, decoupling capacitors and high-frequency ceramic capacitors.

The problem of power integrity refers to that the power distribution network in high-speed systems has different input impedances at different frequencies, resulting in voltage jitter △V caused by noise current △I and transient load current △I' on the power supply/ground plane. . This voltage fluctuation, on the one hand, affects the plane to provide a stable voltage reference for the digital signal, on the other hand, it will cause the provided power supply voltage to jitter and affect the performance of the device. When the plane voltage fluctuation exceeds the tolerance range of the device, the system will not work normally. The key to the design of the power distribution system is the target impedance Z, which is defined as formula (1):

In the formula, Vdd is the chip power supply voltage, ripple is the voltage fluctuation allowed by the system, and △Imax is the maximum transient current change of the load chip. The purpose of the power supply system is to be able to provide sufficient drive current with a constant voltage value within a limited response time, so it needs to have a sufficiently low power supply impedance.

1.2 Methods to solve power integrity

Voltage regulation modules, power/ground planes, decoupling capacitors and high-frequency ceramic capacitors play a decisive role in the impedance of the power distribution system in different frequency ranges. In the low frequency range of 1KHz to a few Hz, the voltage adjustment adjusts the output current to adjust the load voltage; in the mid-range frequency range of a few MHZ to hundreds of MHZ, the power supply noise is mainly filtered by the decoupling capacitor and the power/ground plane pair of the PCB; above 1 GHz In the high frequency part, the power supply noise is mainly filtered by the power/ground plane pair of the PCB and the high frequency capacitor inside the chip. When doing power integrity simulation, the really meaningful frequency band is mainly in the frequency band of several MHZ to several hundred MHZ. At present, there are two main ways to solve the problem of power integrity:

One is to optimize the stack design and layout of the PCB. In high-speed PCB design, the entire copper layer is usually used as a power/ground plane to minimize the input impedance. The power supply and the ground plane can be regarded as a plane capacitor, especially in the low intermediate frequency stage, the equivalent series resistance and equivalent series inductance are very small, and it has good decoupling and filtering characteristics. Integrating the impedance matching done by the signal integrity in the early stage and the current production standards, reasonably setting the interlayer spacing, and selecting the appropriate inter-board capacitance value, can well improve the power integrity of the high-speed design. The capacitance value of the power supply and the ground plane can be estimated as formula (2):

In the formula, εo=8.854 pF; εr=4.5 (FR-4 material calibration value); A is the copper area of the power layer (m2); d is the interval between the copper power layers (m). According to the simulation results, the smaller planar capacitor C has a higher impedance response curve and a higher resonance frequency.

The second is to arrange decoupling capacitors. This is currently the most effective way to solve power integrity problems. In high-frequency systems, the parasitic inductance in the power distribution system cannot be ignored, it directly leads to an increase in the impedance of the power distribution system. Since capacitance and inductance have opposite characteristics in the frequency domain, the method of adding capacitance can be used to reduce the increase in impedance caused by inductance. At the same time, the capacitor has an energy storage effect and can respond to changing current demand at a very fast speed, so it can effectively improve the transient response capability of the power supply in a local area. How to choose a capacitor with an appropriate capacitance value and determine the proper placement of the capacitor so that the impedance of the power distribution system is less than the target impedance within the entire operating frequency range of the PCB system has become the key to solving the problem of power integrity. With the help of Cadence PI, the capacitance, quantity and placement of decoupling capacitors can be quickly determined to improve development efficiency.

2 Power integrity simulation

2.1 ARM11 core system

In this article, Cadence PI is used as a simulation tool to analyze the power integrity of the ARM11 core system. The ARM11 core system in this article uses the S3C6410 chip. S3C6410 is an ARM11 architecture, FBGA package, and a chip that requires multiple power supplies. In this article, the chip has 2 working voltages: 1.2 V core power supply, 26 power supply pins (10 core power supply pins, 16 logic power supply pins); input/output interface power supply 3.3 V, there are 30 I/O power supply pin. The working frequency inside the chip is 667 MHz, and the working frequency of the external memory input/output interface is 266 MHz. The ARM11 core system adopts an 8-layer stack structure, and the spacing between layers is set under the premise of signal simulation impedance matching and production standards. This article uses Cadence PI to simulate the power integrity of the ARM11 core voltage power supply network VDD_ARM.

According to the S3C6410 chip data manual, the core current consumption is 200 mA, plus 100% tolerance, the allowable voltage fluctuation value of the system is 4%, and the core voltage is 1.2V. According to formula (1), the target impedance is set in the simulation It is 0.12 Ω.

2.2 Power integrity simulation

2.2.1 Single node simulation, analysis, verification and optimization of capacitor selection

In single-node simulation, the actual physical connection of each component in the power system is ignored. Assuming that the power supply voltage regulating module VRM, simulation excitation source, current source, and all capacitors are connected in parallel, single-node simulation can obtain what is needed to maintain the target impedance Capacitance.

2.2.2 Multi-node simulation, placement of decoupling capacitors to optimize layout

Since the single-node simulation does not consider the layout of the decoupling capacitors, in order to obtain more accurate results, consider the placement of noise sources and decoupling capacitors, and perform multi-node simulations in the full frequency range. In multi-node simulation, Cadence PI divides the power plane into multiple grids according to user definitions and models each grid. Then, the placed decoupling capacitor, voltage regulation module VRM, and noise source are connected to the specific grid. The grid points are connected to generate the frequency-impedance simulation waveform of each node.

In order to obtain higher accuracy, the grid size must be larger than 1/10 of the wavelength corresponding to the highest frequency of the system.

2.2.3 Analysis of the static IR-Drop DC voltage drop of the power plane

For the chip to work normally, the power supply voltage must be limited within the allowable fluctuation range. Power fluctuations are caused by two parts: DC loss and AC noise. DC IR-Drop is the main cause of DC loss. The static IR-Drop DC voltage drop is mainly related to the width of the metal connection and the layer used, the current flowing through the path, the number and location of the vias. After setting the power supply pins and sink current in Cadence PI, analyze the DC voltage drop of the ARM11 core power supply voltage network VDD_ARM after the layout is completed. When the operating frequency of the ARM11 core system is 667 MHz, its 1.2 V DC voltage The allowable fluctuation range is +/-0.05 V. Cadence PI simulation software calculates the voltage gradient of the VDD_ARM network. The maximum value of Drop is 0.013 V, which is less than the allowable fluctuation range of +/-0.05 V, which fully meets the operating voltage requirements of S3C6410 and can ensure the stability of the system.

2.2.4 Power plane current density analysis

When there are too many vias or unreasonable distribution on the power plane, current will flow through a narrow area, resulting in excessive current density in this area. The largest current density area on the power plane is called a hot spot. The hot spot may cause serious thermal stability problems. Therefore, it is necessary to design the vias reasonably to make the current density distribution of the board uniform, and avoid near key chips and high-speed traces. Hot spots appear.

3. PCB power integrity test

In the first version of the PCB, Cadence PI analysis was not used, but some decoupling capacitors were placed based on experience. During debugging, it was found that the waveform of the high-speed digital signal was not good, and sometimes there were errors. In the second edition, through Cadence PI analysis, the number and position of decoupling capacitors, and the layout of some originals were adjusted.

The 1.2 V switching power supply provides an output current of about 0_2～0.8A for the power plane. When the dynamic load is at a constant voltage, the output impedance changes periodically, and the current amplitude can complete a jump of 0.2～0.8 A in the same cycle. It can be seen from the data that the power integrity of the second version PCB produced after Cadence PI analysis has been greatly improved.

4. Conclusion

After the simulation analysis of Cadence PI, the ARM11 core system PCB board was produced. Through actual measurement of the circuit, it was found that each power distribution system can work very well, which is basically consistent with the simulation results. With the high-speed increase of system frequency, the power distribution system becomes more complex, and the engineering production cost and cycle are strictly controlled. When designing electronic systems, power integrity simulation analysis is performed at the system level to simulate the behavior of the real system, which improves design efficiency and reduces Design errors are necessary.