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Use Serial RapidIO Exchange to Handle the Signal Integrity of High-Speed Circuit Board Design
2021-08-24
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Author:IPCB

The signal integrity (SI) problem is becoming an issue of increasing concern for digital hardware designers. As wireless base stations, wireless network controllers, wired network infrastructure, and military avionics systems have increased data rate bandwidth, circuit board design has become increasingly complex.


At present, high-speed serial links between chips have been widely used to improve overall throughput performance. The processor, FPGA, and digital signal processor can transmit large amounts of data to each other. In addition, the data may have to be sent from the circuit board and transmitted through the backplane to the switch card, and the switch card can send the data to other cards in the chassis or elsewhere in the "system". The exchange that supports RapidIO can realize the interconnection between these different components, and is widely used to meet the real-time bandwidth requirements of these applications.


This article mainly discusses the signal integrity problems related to high-speed interface design (the main function of RapidIO switching supports these high-speed interface designs) and other related matters. The optimization of the function of RapidIO switching is to achieve higher signal integrity in high-speed designs.


High-speed interface design challenges


Signal quality is very important to all aspects of the system. For serial RapidIO, the signal quality is quantified by the size of the received eye diagram. The receiving eye diagram is an infinitely continuous trajectory, in which the waveform will repeat with the previous trajectory. The larger the eye diagram opens, the better the signal quality.


Signal quality may be affected in many ways: noise or other messy signals in the signal channel, poor signal channel wiring, conduction or radiation from external sources, and noise generated by the system itself. The combination of all the above factors will cause the receiving eye diagram to shrink. In addition to board-level issues, signal integrity may also be affected by the source (transmitting end) and destination (receiving end) of the connection. Therefore, the source and destination IC characteristics should be considered in the overall system-level signal integrity.


Considerations for board-level design


As far as circuit board design is concerned, common factors that should be considered include:


1. The power input of the circuit board, the output and distribution of the local regulator

2. Clock generation and distribution

3. Decoupling

4. PCBbasic materials

5. Chip-to-chip connection

6. Connection between circuit boards and backplane connection

7. Circuit board stacking and impedance control

8. Inter-rack connectors, cables and connectors


When the operating frequency is higher than 300MHz, most of the design best practices that apply to lower frequency circuit board designs need to be modified. The factors that arise when the wavelength is comparable to the size of the circuit board must be considered. This applies not only to the wavelength of the fundamental frequency, but also to the Fourier (frequency domain) components that make up the complete waveform.


FR4 material can still be successfully used as a basic material for circuit boards, but at higher frequencies, not only the dielectric constant of the material needs to be considered, but also the loss factor. The design of the vias has also become very important, because the impedance of the unused tube length (which has a negligible effect at lower frequencies) will not match the impedance of the thicker circuit board and backplane. It is best to complete a post-design simulation to draw attention to wiring with less than ideal signal integrity and to point out crosstalk areas.


The specific problems of signal integrity on the circuit board are caused by the existence of high-speed processor bus and high-speed memory interface, clock generation and clock noise, and various circuit board noise sources, usually including: single-ended parallel bus, power distribution, impedance Matching, ground bounce, crosstalk and clock generation.


Serial RapidIO Switch


Serial RapidIO interconnect can be used to deal with some of the signal integrity problems discussed above. RapidIO is a mature and open standard for interconnection between chips, circuit boards, and chassis. It is designed by leading manufacturers in the field of embedded computing to meet the needs of equipment in the wireless infrastructure, network, storage, scientific, military, and industrial markets. Reliability, cost-effectiveness, performance and scalability requirements.


RapidIO is a point-to-point data packet switching interconnection protocol designed to meet the needs of current and future embedded applications. The RapidIO physical layer 1x/4x link serial specification can meet the physical layer media requirements of devices that use electronic serial connections. This specification defines a full-duplex serial physical layer interface (link) between devices that use unidirectional differential signaling. In addition, for applications that require higher link performance, it also allows four serial links to be combined. It also defines the protocol for link management and data packet transmission through the link.


The architecture of the RapidIO system consists of endpoint components and a switching structure that connects the endpoints. Imagine the endpoint as the starting point in the mail system, and the switch as the post office that intercepts the package and sends it to the destination. The RapidIO interconnect architecture is divided into a layered architecture according to the specification, including a logical layer, a common transport layer, and a physical layer. The physical layer of the RapidIO protocol is processed by the chip serializer-deserializer (SerDes). The characteristics of SerDes have a certain impact on the signal integrity problems faced by hardware designers when designing circuit boards. Many other aspects of switch design will also affect signal integrity.


The characteristics of RapidIO switching simplifies circuit board design and achieves high signal integrity


Clock generation


As far as the initiator is concerned, the sRIO switch must have a noise-free clock signal that achieves low jitter. The low jitter signal basically has the characteristics of low phase noise. If the input clock signal is increased to achieve a higher frequency output signal, the chip circuit must be optimized to produce the smallest phase noise. Tundra’s Tsi57x serial RapidIO switches generate output signals up to 3.125Ghz by using 125MHz and 155MHz clocks with integrated low-noise amplification PLL. Many products use independent circuits to achieve the above functions, so they cannot achieve low jitter like Tundra switching chips. The clarity of the output signal is not as good as when using Tundra switching chips, making it difficult for the circuit board design to tolerate other board-level signal integrity issues discussed above.


Programmable transmission pre-emphasis and receiver equalization


In the design of high-speed circuit boards, since the signal is transmitted from the chip to the chip through the circuit board or through the backplane, signal attenuation needs to be considered. In short, the actual signal will decrease in strength when it reaches the end point, and phase shift may occur. Generally, in all media, higher frequency harmonics have a greater proportion of lower frequency harmonics attenuation. Enhancing the overall signal is not enough, because it enlarges the noise floor and does not solve the phase shift problem. Serial RapidIO switches and endpoints (like all other high-speed designs such as GbE and 10GbE) utilize technology to avoid this problem and maintain the integrity of the original signal.

ATL

To understand the effects of transmission pre-emphasis and receiver equalization, you can review the eye diagrams. The goal is to achieve "eye-opening". If these techniques are not used, the eye diagram will begin to "close".


Transmission pre-emphasis technology can add high frequency to the transmission signal to solve the problems of signal attenuation and phase shift between endpoints. Therefore, instead of simply amplifying all frequencies (this method will also increase the overall power consumption of the switching chip), transmission pre-emphasis can effectively enhance the output waveform through the transmission function, increase the high frequency of the output waveform, and use virtual components to control it. Perform phase shift to solve the phase shift caused by the transmission medium. This method is quite effective for maintaining signal integrity and maintaining eye diagrams.


Although transmission pre-emphasis is usually applied in many high-speed ICs to optimize overall system-level signal integrity, transmission pre-emphasis at the "transmitting end" should be used in conjunction with receiver equalization at the "receiving end". The receiver equalization uses the enhancer transmission function to compensate for the high-frequency transmission loss and phase shift caused by the circuit board and backplane. Since these transmission losses occur before the signal reaches the destination IC (in this article, the serial RapidIO switch), usually the switch must take measures before the signal is sent to the next transmission part (another switch) or endpoint in the system Compensate for these losses. The effect of receiver equalization is similar to that of transmission pre-emphasis, which can improve the overall signal-to-noise ratio. Note: Each link connected to the switch chip may have different characteristics.


Similarly, the receiver equalization needs of each link will be different and need to be programmed before it can be used. All Tundra RapidIO Tsi57x switches have this feature, and in terms of signal integrity, this feature will greatly simplify system-level design.


Synchronous and asynchronous exchange design


The serial RapidIO standard supports three different link rates: 1.25G baud, 2.5G baud and 3.125G baud. Exchanges can be divided into two categories: synchronous and asynchronous.

Synchronous switching refers to switching in which all ports must operate at the same speed.

Asynchronous switching refers to the switching in which each port can operate at the frequency required by the traffic demand of a specific link.


In most applications, the best solution is asynchronous switching, which not only has the advantage of meeting the demand for communication with lower overall system power consumption, but also has less impact on crosstalk in terms of signal integrity.


Packaging and interconnection


Signal integrity issues may be largely affected by the packaging and basic material design. For example, high-performance flip-chip and wire bond packaging can improve power transmission and reduce return loss. For RapidIO switches, it is important to improve impedance matching to maintain 100 ohm differential impedance and low variation. Flip chip packaging can help improve the above situation.


Efficient spherical mapping


Silicon chip suppliers may choose spherical mapping to simplify the signal transmission from the chip to the ball grid, but its role is not limited to this. In an ideal situation, the overall system-level implementation will be considered when designing the spherical map. For example, when designing a spherical map, remember to link the peripheral IC to the switch chip. The design should be optimized to minimize the number of layers and the required area, which can improve the signal integrity of the final design. An IC equipped with a fairly dense spherical mapping requires many layers on the circuit board to send the signal out of the IC, leading to a high-cost system-level design. Another problem is the crosstalk between signal channels, which was mentioned in the discussion of the difference between synchronous and asynchronous RapidIO exchanges above. A problem closely related to crosstalk between signal channels and efficient spherical mapping is the spacing between the power and ground pins. If too many serial RapidIO ports are inserted into a small package, it may cause signal integrity problems due to crosstalk, which can lead to "closed eyes" when the signal is transmitted from the switch to the endpoint.


Design convention skills


Now, let’s review another aspect of signal integrity, which is the board-level design issue. Designers can take many design guidelines to control the effects of noise. Generally, good design practices can help circuit board designers control the signal noise generated by board-level communications, including limiting external noise sources and solving the noise of the device itself.


First, all designs should use the correct trace width, spacing, and topology to ensure that the impedance of each trace matches its transmission device. Impedance mismatch may affect the quality of the leading and trailing edges, settling delay time, crosstalk, and EMI.


It is necessary to ensure that there is sufficient channel spacing between the synchronization signal groups, and the channel length must be limited and the offset between the differential pair signals must be minimized. When wiring, the number of wiring layer transitions should be minimized to limit parasitic effects. The cost of vias in unnecessary inductance and stray capacitance is very high and should be minimized. Except for BGA pads, each channel usually allows up to two vias.


Thorough verification of signal integrity is crucial. Using estimated parasitics, pre-design analysis can provide the data needed to understand design performance, but accurate post-design parasitics can provide the details needed to discover potential signal integrity issues. Using this method, a circuit netlist can be created for simulation and the results recorded.


If the channel and signal channel are shortened as much as possible, shielded by a ground layer or physically separated from each other, and pay attention to avoid impedance mismatch or any configuration that causes resonance, good signal integrity can be obtained.


Choose serial RapidIO switch chip to achieve higher signal integrity


How do designers choose serial RapidIO switches? Just as good design practices can help circuit board designers control the signal noise generated by circuit board-level communications, hardware designers need to actively consider the characteristics of clock generation, transmission pre-emphasis and receiver equalization, optimized packaging technology, effective spherical mapping, and The asynchronously designed serial RapidIO switch can ensure the high signal integrity of the system-level design. Obviously, when choosing a serial interface, the chip chosen by the designer must not only have the appropriate functions, but also a switching chip designed to solve the problem of high-speed signals.


At present, Tundra Semiconductor Corporation can provide three generations of serial RapidIO switching products with the above characteristics. The Tsi 57x product line includes Tsi574, Tsi576 and Tsi578. The number of ports varies from 4 to 16 ports, and the operating speed ranges from 1.25G to 3.125G. Each port supports x1 and x4 channels to choose from, and the power consumption of each port is 120 to 200mW. The Tsi57x product line has all the signal integrity features described in this article, including transmission pre-emphasis and receiver equalization. Compared with the previous Tsi56x product line, this product has added some new functions, including multicast function and matrix performance monitoring. In addition, many advanced communication management functions have been optimized to meet the high-performance requirements of applications such as wireless base stations, wireless network controllers, wired network infrastructure, and military avionics systems.


Summary of this article


Through the above analysis, it can be found that if you are familiar with the basic design rules, any traditional problems related to poor signal integrity, such as noise, transient effects, crosstalk or jitter, can be avoided when high-frequency interconnections (such as serial RapidIO) are used in the system. .