Ultra-precision PCB Fabrication, High Frequency PCB, High Speed PCB, IC Substrate, Multilayer PCB and PCB Assembly.
The most reliable PCB custom service factory.
PCB Tech

PCB Tech

PCB Tech

PCB Tech

Encapsulation term explanation

Explanation of IC packaging terms (1)
1. BGA (ball grid array)
A display of spherical contacts, one of the surface mount packages. On the back of the printed circuit board, spherical bumps are made according to the display method for
Instead of pins, an LSI chip is mounted on the front side of the printed circuit board, and then sealed with molded resin or potting. Also called convex
Point display carrier (PAC). Pins can exceed 200, which is a package for multi-pin LSI.
The package body can also be made smaller than QFP (Quad Flat Package). For example, 360 pins with a pin center distance of 1.5mm
BGA is only 31mm square; while the 304-pin QFP with a pin center distance of 0.5mm is 40mm square. And BGA doesn’t
Worry about pin deformation like QFP.
This package was developed by Motorola Company of the United States. It was first adopted in portable phones and other devices, and will be available in the United States in the future.
Can be popularized in personal computers. Initially, the BGA pin (bump) center distance was 1.5mm, and the number of pins was 225. Now also
Some LSI manufacturers are developing 500-pin BGAs.
The problem with BGA is the visual inspection after reflow soldering. It is not yet clear whether an effective visual inspection method is available. Some think,
Due to the large center distance of welding, the connection can be regarded as stable and can only be processed through functional inspection.
American Motorola Company refers to the package sealed with molded resin as OMPAC, and the package sealed by potting method is called
GPAC (see OMPAC and GPAC).

2. BQFP (quad flat package with bumper)
Four-side pin flat package with cushion. One of the QFP packages. Protrusions (buffer pads) are provided at the four corners of the package body to
Prevent bending and deformation of the pins during transportation. American semiconductor manufacturers mainly use microprocessors and ASICs in circuits
This package. The pin center distance is 0.635mm, and the pin number is about 84 to 196 (see QFP).

3. Butt welding PGA (butt joint pin grid array)
Another name for surface mount PGA (see surface mount PGA).

4. C-(ceramic)
Indicates the mark of the ceramic package. For example, CDIP stands for ceramic DIP. It is a mark that is often used in practice.

5. Cerdip
Ceramic dual in-line package sealed with glass, used for ECL RAM, DSP (digital signal processor) and other circuits. With
Cerdip of glass window is used for ultraviolet erasable EPROM and microcomputer circuit with EPROM inside. Pin Center
The distance is 2.54mm, and the number of pins is from 8 to 42. In Japan, this package is expressed as DIP-G (G means glass seal).

6. Cerquad
One of the surface mount packages, the ceramic QFP under hermetic sealing, is used to package logic LSI circuits such as DSP. With window
Cerquad of the port is used to encapsulate EPROM circuits. The heat dissipation is better than plastic QFP, and it can tolerate 1.5~under natural air cooling conditions
2W power. But the packaging cost is 3 to 5 times higher than that of plastic QFP. The pin center distance is 1.27mm, 0.8mm, 0.65mm, 0.5mm,
Various specifications such as 0.4mm. The number of pins ranges from 32 to 368.

7. CLCC (ceramic leaded chip carrier)
A ceramic chip carrier with pins, one of the surface mount packages. The pins are drawn from the four sides of the package and are in a T-shape.
It is used to encapsulate the ultraviolet erasable EPROM and the microcomputer circuit with EPROM with windows. This package is also called
QFJ, QFJ-G (see QFJ).

8. COB (chip on board)
Chip-on-board packaging is one of the bare chip mounting technologies.
The electrical connection of the board is realized by the wire stitching method, and the electrical connection between the chip and the substrate is realized by the wire stitching method, and it is covered with resin.
Cover to ensure security. Although COB is the simplest bare chip mounting technology, its packaging density is far inferior to TAB and rewind
Welding technology.

9. DFP (dual flat package)
Double-sided lead flat package. It is another name for SOP (see SOP). There used to be this term, but it is basically not used now.

10. DIC (dual in-line ceramic package)
Another name for ceramic DIP (including glass seal) (see DIP).

11. DIL (dual in-line)
Another name for DIP (see DIP). European semiconductor manufacturers often use this name.


12. DIP (dual in-line package)
Dual in-line package. One of the plug-in packages, the pins are drawn from both sides of the package, and the package materials are plastic and ceramic.
DIP is the most popular plug-in package, and its application range includes standard logic ICs, memory LSIs, and microcomputer circuits.
The pin center distance is 2.54mm, and the number of pins is from 6 to 64. The package width is usually 15.2mm. Some have a width of 7.52mm
And the 10.16mm packages are called skinny DIP and slim DIP (narrow DIP) respectively. But in most cases, no distinction is made.
Simply collectively referred to as DIP. In addition, ceramic DIP sealed with low-melting glass is also called cerdip (see cerdip).

13. DSO (dual small out-lint)
Two-sided lead small outline package. Another name for SOP (see SOP). Some semiconductor manufacturers use this name.

14. DICP (dual tape carrier package)
Two-sided lead-carrying package. One of TCP (Tape Carrier Package). The pins are made on the insulating tape and lead out from both sides of the package. Due to benefit
It uses TAB (automatic tape load welding) technology, and the package outline is very thin. It is often used in liquid crystal display driver LSI, but most of them are customized products.
In addition, the 0.5mm thick memory LSI book package is in the development stage. In Japan, according to EIAJ (Electronic Mechanics of Japan)
The industry association standard stipulates that DICP is named DTP.

15. DIP (dual tape carrier package)
Same as above. The Japanese Electronic Machinery Industry Association standard names DTCP (see DTCP).

16, FP (flat package)
Flat package. One of surface mount packages. Another name for QFP or SOP (see QFP and SOP). Some semiconductor manufacturers adopt
Use this name.

17, flip-chip
Flip-soldering the chip. One of the bare chip packaging technologies, metal bumps are made in the electrode area of the LSI chip, and then the metal bumps
It is connected to the electrode area on the printed circuit board by pressure welding. The footprint of the package is basically the same as the chip size. Is all packaging technology
The smallest and thinnest type in surgery.
However, if the thermal expansion coefficient of the substrate is different from that of the LSI chip, there will be a reaction at the junction, which will affect the reliability of the connection.
Sex. Therefore, it is necessary to use resin to reinforce the LSI chip, and use a substrate material with substantially the same thermal expansion coefficient.

18. FQFP (fine pitch quad flat package)
Small pin center distance QFP. Usually refers to a QFP with a lead center distance less than 0.65mm (see QFP). Part of the conductor manufacturer adopts
Use this name.

19. CPAC (globe top pad array carrier)
American Motorola Company's nickname for BGA (see BGA).

20, CQFP (quad fiat package with guard ring)
Four-side lead flat package with guard ring. One of the plastic QFPs, the pins are masked with a resin protection ring to prevent bending and deformation.
Before assembling the LSI on the printed circuit board, cut the lead from the guard ring and make it into a seagull wing shape (L shape). This package
It has been mass-produced by Motorola in the United States. The pin center distance is 0.5mm, and the number of pins is about 208 at most.

21, H-(with heat sink)
Indicates a mark with a radiator. For example, HSOP means SOP with heat sink.

22, pin grid array (surface mount type)
Surface mount PGA. Usually PGA is a plug-in package with a pin length of about 3.4mm. Surface mount PGA in the package
There are display-like pins on the bottom, the length of which is from 1.5mm to 2.0mm. Mounting uses the method of touch-welding with the printed circuit board, so it is also called
For butt welding PGA. Because the pin center distance is only 1.27mm, which is half smaller than that of the plug-in type PGA, the package body can be made differently.
How large, and the number of pins is more than that of the plug-in type (250~528), it is a package for large-scale logic LSI. The encapsulated substrate has multilayer ceramics
Porcelain substrate and glass epoxy resin printing base. The packaging of multilayer ceramic substrates has been put into practical use.

23, JLCC (J-leaded chip carrier)
J-shaped pin chip carrier. Another name for CLCC with window and ceramic QFJ with window (see CLCC and QFJ). Part and half
The name adopted by the conductor manufacturer.

24, LCC (Leadless chip carrier)
Leadless chip carrier. Refers to a surface-mount package in which the four sides of the ceramic substrate are only in contact with electrodes without leads. Is high
High-speed and high-frequency IC packages, also known as ceramic QFN or QFN-C (see QFN).

25, LGA (land grid array)
Contact display package. That is, a package with array state electrode contacts is made on the bottom surface. Just plug in the socket when assembling. Now
Practical ceramic LGA with 227 contacts (1.27mm center distance) and 447 contacts (2.54mm center distance) for high-speed logic
LSI circuit.
Compared with QFP, LGA can accommodate more input and output pins in a smaller package. In addition, due to the impedance of the lead
Small, very suitable for high-speed LSI. However, due to the complicated production and high cost of sockets, they are basically not used much now. Expected
Its demand will increase in the future.

Explanation of IC packaging terms (2)

26, LOC (lead on chip)
Lead-on-chip packaging. One of the LSI packaging technologies, a structure in which the front end of the lead frame is above the chip, and the chip’s
Protruding solder joints are made near the center, and wire stitching is used for electrical connection. Compared with the original lead frame placed near the side of the chip
Compared with the structure, the chip contained in the same size package is about 1mm wide.

27, LQFP (low profile quad flat package)
Thin QFP. Refers to the QFP with a package body thickness of 1.4mm, which is a new QFP formulated by the Japanese Electronic Machinery Industry Association
The name used for the form factor.

28, L-QUAD
One of ceramic QFP. Aluminum nitride used for packaging substrates has a thermal conductivity 7-8 times higher than that of aluminum oxide, and has better heat dissipation.
The frame of the package is aluminum oxide, and the chip is sealed by potting, thereby suppressing the cost. Is a package developed for logic LSI,
Allowable W3 power under natural air cooling conditions. 208-pin (0.5mm center distance) and 160-pin (0.65mm
Center distance) LSI logic package, and started mass production in October 1993.