PCB Tech - Signal integrity verification case analysis

Questions about signal integrity are discussed with most circuit board design engineers, and they will talk endlessly, telling you how complicated and dangerous designing high-speed circuit boards is. They will tell you that when the system clock exceeds 50MHZ, the signal interconnection on the board will introduce signal delays in the timing path, and these signal delays will restrict the performance of the board-level design. They will also describe to you how transmission line effects will quickly introduce serious signal integrity problems such as signal oscillation, overshoot, and undershoot, and how these problems will threaten the design's noise tolerance and the design's monotonic consistency principle. . What's more, the appearance of signal crosstalk and electromagnetic radiation will seriously damage the normal operation of the designed circuit board.

The same question may get different answers. If you are in contact with engineers who are still working on low-speed circuit board design, they usually just shrug their shoulders to show helplessness. The traditional strategy of passive response to potential signal integrity problems in low-speed circuit board design is to formulate appropriate design constraints for the design. When some special signal channels have serious signal integrity problems such as signal crosstalk or electromagnetic interference, usually design engineers always add strict physical constraints to a certain part of the design or even the entire design itself.

Even if this kind of solution can still meet the temporary needs, design engineers have to pay a high price for this. Constraint design usually increases the final product cost and restricts product performance. For example, design engineers may be forced to increase the signal board layer because they cannot find a suitable location to realize a certain signal interconnection. However, in today's highly fierce market competition, whether the cost can be minimized and whether it can provide unique product performance often means the success or failure of the product.

Recently, a design engineer from a well-known network equipment provider used the signal integrity analysis tool set XTK developed by Innoveda to perform signal analysis on a circuit board on the router product they developed. The results of the analysis are shocking. Although the circuit board works normally, the very strict design rules result in the implementation of the circuit board design requiring 24 circuit board layers to avoid signal integrity problems. The analysis results show that the design is seriously over-constrained. In fact, the circuit board design only needs 8 circuit board layers to be processed and realized, and at the same time, it will not interfere with the signal integrity problem. The improved product saves up to two million US dollars in the production cost of the circuit board alone.

Many design engineers find that signal integrity analysis is no longer just a special problem in the field of high-speed system design. The real cause of signal integrity problems is the ever-decreasing signal rise time and signal fall time rather than the increase in the system clock. With the continuous advancement of IC manufacturers' production process technology, the current technical level has reached 0.25um process or even lower. Continuously improving component production technology is used to eliminate outdated and outdated technologies. When traditional standard electronic components are manufactured using advanced technology, the size can be made smaller, and at the same time, the switching speed of the device has become more and more. The faster, so the rise time and fall time of the signal become shorter and shorter.

In fact, about every three years, the size of the transistor gate will be reduced by about 30%, and accordingly, the switching speed of the transistor will increase by about 30%. The reduction of signal rise time and fall time will lead to a "potential crisis", which will eventually lead to high-speed problems in the design, which has never been regarded as a factor that causes high-speed problems in the traditional design process.

Why is it said that faster signal edge transitions (shorter signal rise time and signal fall time) rather than the increase in system clock frequency have brought serious and significant design challenges to circuit board design engineers? This is because when the signal transition is relatively slow (the rise time and fall time of the signal are relatively long), the wiring in the PCB can be modeled as an ideal wire with a certain amount of delay to ensure a fairly high accuracy. For functional analysis, all the in-line delays can be lumped at the output of the driver, and the input terminals of all receivers connected to the output of the driver through different in-line segments will observe the same signal at the same time. Waveform.

The lumped delay parameter model can accurately analyze the circuit behavior without special simulation analysis. Practice shows that if the delay factor of the lumped parameter is considered in the design, the physical realization is very close to the theoretical analysis and simulation.

As the signal changes faster (signal rise time and fall time are shortened), each wiring segment on the circuit board is transformed from an ideal wire to a complex transmission line. At this time, the delay of the signal connection can no longer be modeled on the output end of the driver in the way of a lumped parameter model. At this time, when the same driver signal drives a complex PCB connection, the signals received on each receiver that are electrically connected together are different. Not only the signal delay of the entire PCB connection needs to be split into the signal delays of their respective PCB connection segments, but also the mutual influence of various transmission line effects on each PCB connection segment must be carefully considered. Due to the high-speed effects, it is difficult for design engineers to predict the signals on complex PCB connections. Therefore, transmission line analysis is required to determine the actual delay of the signal at the input of each receiver.

It is known from practical experience that once the length of the transmission line is greater than 1/6 of the effective length corresponding to the rise time or fall time of the driver, the effectiveness of the transmission line will appear. For example, assuming that the rise time of the components used in the design is 1ns, and the signal transmission speed on the PCB connection line is 2ns/ft, then as long as the length of the connection line exceeds 1 inch, transmission line effects will appear, potentially high-speed Circuit problems may appear. Obviously, the length of all the wires on the board is less than 1 inch. There are few circuit boards. Based on this understanding, it is conceivable that design engineers will encounter high-speed issues when designing with components with a rise time of 1ns.

With the continuous updating of IC process technology, the above-mentioned problems are getting worse and worse.

In today's system design, devices with a rise time of 1 ns have quickly become a thing of the past. PC design engineers are using high-performance processors with a rise time of 0.5ns to achieve a complex system design such as a clock speed exceeding 400MHZ and a bus operating frequency exceeding 100MHZ. These design engineers already have experience in high-speed circuit design, so they will consider special issues in high-speed design. However, high-speed design problems have become more and more popular. As long as design engineers use a new generation of FPGA devices with 0.25um process technology or other standard components to design new products, these high-speed problems will be numerous. Existence, if certain types of high-speed analysis are not implemented, the designed system is difficult to work properly.

Signal transitions rather than the continuous acceleration of the clock frequency in the design will lead to a deteriorating design environment: smaller and smaller design fault tolerances, and any subtle differences in the design may lead to potential problems. I cannot fail to mention an incident that happened recently in a well-known American manufacturer of machine vision systems. This is a well-known manufacturer of machine vision systems (image detection systems) in the United States. Recently their circuit board design engineers encountered a very strange phenomenon. A product that has been successfully designed, manufactured, and put on the market as early as seven years ago has been able to run and work very stably and reliably. However, a product that has been rolled off the production line recently has problems and the product does not work properly.

This is a 20MHz system design. It seems that there is no need to consider high-speed design issues. There is no design modification, and the components used are consistent with the original design requirements. The design engineer feels very confused: Why does the system fail? Without any design modification, the manufacturing is based on the same electronic components in the original design. The only difference is that the electronic components used have achieved miniaturization and faster, which is mainly due to the continuous advancement of today's IC manufacturing technology. So what caused the failure of the system?

Facts have proved that the failure of the system is due to the signal integrity problems introduced by the new device process technology. These problems have not been encountered by the design engineer in the original verified relatively low-speed system and do not need to be considered. Signal integrity problems can be expressed in different ways. Timing issues always come first. The shortening of signal rise time and fall time will first cause timing issues in the designed system. Secondly, the signal oscillation, signal overshoot and undershoot caused by the transmission line effect will all pose a great threat to the fault tolerance and monotonicity of the designed system. In slow systems, interconnection delays and signal oscillations are often ignored by design engineers, mainly because signal oscillations caused by transmission line effects have enough time to stabilize in slow systems. However, with the continuous acceleration of signal jumps and the continuous improvement of system clock frequency, the time for signal transmission between devices and preparation for clock control is greatly shortened. The severity of the problem has suddenly increased, and the probability of failure has also increased rapidly.

Some problems with high-speed circuits are not very serious, while others are catastrophic. For example, the signal oscillation caused by the establishment of the back and forth reflection of the signal on the transmission line may cause false triggering of the device (multiple clock control). The signal overshoot mainly due to signal reflection will cause timing errors and may even damage components. After the rise time of the signal drops below 1ns, the crosstalk between the signals becomes a very important issue. Crosstalk usually occurs in high-density circuit board designs. At the same time, the signal jumps very fast, and it is very easy to couple between lines to form crosstalk. When the signal rise time is less than 1ns, the high-frequency harmonic components in the signal are easily coupled to adjacent signal lines to form crosstalk. Therefore, if there are a large number of high-speed interconnection signal lines in the circuit board, such a system is prone to problems in this regard. The emergence of high-speed devices makes the rise time of the signal less than 0.5ns, leading to more problems in the designed system: stability problems of the power system and electromagnetic interference (EMI) problems. When the frequency of simultaneous data changes on the data bus is very high, the stability of the power system may occur, which leads to large fluctuations and fluctuations in the power plane. Large fluctuations and fluctuations in the reference plane in the system will affect the signal in the design. This type of system design requires careful planning of the power system design and selection of the most reasonable power system decoupling strategy. The close combination of the two is the key to ensuring the stability of the power system. Fast signals are also more prone to radiation, so EMI is becoming more and more of the attention of design engineers, and it has become an important aspect that must be considered in new designs. Especially today's electronic products must face many regulations of the industry.

Unfortunately, in low-speed system design, the potential crisis caused by the reduced signal rise time is often overlooked by design engineers. This is because design engineers do not want to perform signal integrity analysis, but avoid it as much as possible. The real danger is that many circuit boards are sent for processing when the signal integrity issues are still unclear. At the same time, due to the unpredictability of the signal integrity problem itself, the signal integrity problem may not be manifested in the final test process of the processed circuit board, and when the product is sent to the end user, the signal integrity problem It may appear. If the product fails on the user site, the diagnosis and solution of the problem will become very difficult. The real risk also lies in higher NRE (one-time engineering costs) costs. Every circuit board product design manufacturer will share all NRE expenses during the product life cycle. After the circuit board is designed and produced, the design iterations caused by unpredictable high-speed signal integrity problems will cause the NRE cost to increase rapidly.

There is a well-known axiom in the field of electronic product design and production: the cost of repetitive work increases exponentially from the design stage to the production stage, and once the product has been distributed to the end user site, the cost of this repetitive work will become higher. . Therefore, any board-level design that can work normally during the design and production process, if there is a problem with the product after it is sent to the user site, compared with the design engineer’s expectation to find and solve the problem in the traditional high-speed design field, the product development is in progress The cost structure will bring greater risks. These costs not only include huge costs directly caused by a large amount of repetitive work, but also reflect user dissatisfaction and loss of confidence. The above issues strongly require the introduction of a new step in the development cycle of any board-level product to prevent signal integrity issues from sneaking into the production process. For many years, ASIC design engineers have formed a good habit. As part of the contract agreement, the ASIC design engineer must sign the "Sign-Off" of the design with the ASIC manufacturer to ensure the integrity of the design information. . In the custom chip development process, the NRE cost invested may be as high as hundreds of thousands of US dollars. IC production and processing manufacturers strongly require that every such design must pass the test of the "golden version" simulator to protect its own cost input and Rights and obligations. In addition, adding the "signature acceptance" step effectively protects and restricts designers and processing manufacturers. It not only requires IC processing manufacturers to produce qualified and high-quality device products for their customers, but also requires IC design engineers to design More standardized, the designed device has a high degree of manufacturability. For circuit board design and processing manufacturers, the Sign-Off of high-speed circuit design (signal integrity verification before the circuit board is sent for processing) is of equal importance. As a step in the conventional design process, high-speed signal integrity verification test tools are used for analysis and verification for each board-level design (regardless of the clock speed in the design). The design engineer must ensure that the signal integrity problems in the design are It has been resolved before sending the design to the manufacturing process. Therefore, design engineers are confident that the products they design have better quality assurance. After the designed product is shipped to the end user site, unpredictable signal integrity problems will no longer occur. In the future, design engineers no longer need to worry about whether they have added appropriate design constraints in order to solve the signal integrity problems in board-level design, or whether they have made every effort to focus on solving key high-speed signal line problems during the design process. Sign-Off verification of signal integrity after circuit board layout can eliminate this risk and engineers’ concerns.

Which type of simulator can provide the best solution for signal integrity analysis and verification of Sign-Off? An ideal simulator can analyze the entire board or a system composed of multiple circuit boards at the same time, instead of only analyzing individual signal lines on the circuit board. Speed is also a very critical factor, and it is very important to complete accurate signal integrity analysis within a reasonable time range. Those SPICE-based signal integrity analysis engines have sufficient analysis accuracy, but the establishment of the analysis takes a long time, and the analysis runs more slowly, so this type of tool is not practical.

The "gold version" simulator must also be able to provide an accurate internal model of the transmission line. With the reduction of signal rise time and fall time, the ideal lossless transmission line model used by many signal integrity analysis engines can no longer meet the requirements of analysis accuracy. At this time, the transmission line should be modeled as a real lossy transmission line model. At the same time, in order to facilitate the solution of the signal integrity problem, a wide and detailed analysis report should be provided, and it can be convenient and detailed to point out specific components or specific interconnection lines. Violation of signal integrity. Finally, such a tool should also have a powerful "What-If" analysis function to help design engineers identify a more appropriate system topology, connection terminal matching scheme, and driver/receiver selection.

In addition, such tools must have sufficient capabilities to solve complex problems such as power plane analysis and design and electromagnetic radiation, and can reveal the relationship between the two and find the most appropriate solution through compromise. Last but not least, this type of tool must support the most advanced models, because the final analysis results ultimately depend on the models used in the analysis.

Ideally, design engineers hope to adopt appropriate strategies to minimize high-speed problems when implementing placement and routing. The implementation of high-speed design methodology will undoubtedly greatly improve the cost-effectiveness of designing products: signal integrity analysis is implemented in the planning stage before placement and routing in the product development cycle. The new generation of EDA technology uses constraint-driven placement and routing methods to help reduce expensive design iterations. For example, the ePlanner tool of Innoveda enables design engineers to think about the prototype of the PCB topology before passing the design down to the subsequent layout and routing process. For example, the ePlanner tool provides a graphical design space detection and interconnection planning and design environment. In this environment, design engineers can implement "What-If" analysis to explore high-speed signal strategies, and establish a router for the downstream routers. Reasonable design rules based on analysis conclusions.

From a long-term perspective, the best solution for high-speed design in the future is to perform signal integrity analysis as early as possible in the design cycle, and to tightly integrate the signal integrity analysis with layout. However, as far as the current situation is concerned, the minimum requirement is that high-speed design Sign-Off (signal integrity verification and testing before the circuit board is sent for manufacturing) must become a standard in every circuit board design process. step.