PCB Tech - Analysis of signal integrity in high-speed circuit design

As the system clock frequency and rise time increase, signal integrity design becomes more and more important. Unfortunately, most digital circuit designers do not realize the importance of signal integrity issues, or do not realize it until the final stage of the design.

This article introduces the influence of signal integrity in the design of high-speed digital hardware circuits. This includes issues such as characteristic impedance control, terminal matching, power and ground planes, signal routing, and crosstalk. Mastering this knowledge allows a digital circuit designer to notice potential signal integrity problems in the early stages of circuit design, and it can also help the design to avoid the impact of signal integrity on design performance.

Although signal integrity has always been one of the necessary design experience for hardware engineers, it has long been ignored in digital circuit design. In the era of low-speed logic circuit design, since signal integrity-related problems rarely occur, the consideration of signal integrity is considered a waste of efficiency. However, as clock rates and rise times have increased in recent years, the necessity and design of signal integrity analysis have also increased. Unfortunately, most designers have not noticed, and still rarely consider the issue of signal integrity in the design.

Modern digital circuits can reach frequencies up to GHz and have rise times within 50ps. At this rate, the negligence on the PCB design trace is even one foot, and the resulting voltage, delay and interface problems will not only be limited to this line, but will also affect the entire board and Adjacent boards.

This problem is particularly serious in hybrid circuits. For example, consider that there is a high-performance ADC in a system to digitally receive analog signals. The energy spread on the digital output port of the ADC device may easily reach 130dB (10, 000, 000, 000, 000 times) than the analog input port. Any noise on the ADC digital port. Signal integrity in design is not a mysterious process. It is critical to realize the potential problems in the early stages of the design, and to effectively avoid the problems caused by this in the later stages. This article discusses some key signal integrity challenges and how to deal with them.

Ensure signal integrity:

1. Isolation

Components on a PCB board have various edge rates and various noise differences. The most direct way to improve SI is to achieve physical isolation of components on the PCB based on the boundary value and sensitivity of the device. The figure below is an example. In the example, power supply, digital I/O ports, and high-speed logic, which are high-risk circuits for clock and data conversion circuits, will be specially considered. In the first layout, place the clock and data converters adjacent to the noisy device. Noise will couple to sensitive circuits and reduce their performance. Effective circuit isolation in the second layout will benefit the signal integrity of the system design.

2. Impedance, reflection and terminal matching

Impedance control and terminal matching are basic issues in high-speed circuit design. Usually the radio frequency circuit is considered to be the most important part in every circuit design, but some digital circuit designs with higher frequency than radio frequency neglect impedance and terminal matching.

There are several fatal effects on digital circuits due to impedance mismatch, see the figure below:

a. The digital signal will cause reflections between the input of the receiving device and the output of the transmitting device. The reflected signal is bounced back and propagates along both ends of the line until it is completely absorbed at the end.

b. The reflected signal causes the ringing effect of the signal passing through the transmission line, and the ringing will affect the voltage and signal delay and the complete deterioration of the signal.

c. Mismatched signal paths may cause signal radiation to the environment.

The problem caused by impedance mismatch can be minimized by terminating resistors. The termination resistor is usually one or two discrete components placed on the signal line close to the receiving end. The simple method is to connect a small resistor in series.

The terminal resistance limits the signal rise time and absorbs part of the reflected energy. It is worth noting that the use of impedance matching cannot completely eliminate destructive factors. However, by carefully selecting the appropriate device, the terminal impedance can effectively control the integrity of the signal.

Not all signal lines need impedance control, such as the characteristic impedance and terminal impedance characteristics of the compact PCI specifications.

For other standards and designers that do not require impedance control specifications, they are not specifically concerned. The final standard may change from one application to another. Therefore, the length of the signal line (correlation and delay Td) and the signal rise time (Tr) need to be considered. The general rule for impedance control is that Td (delay) should be greater than 1/6 of Tr.

3. Inner electric layer and inner electric layer segmentation

The factors that will be ignored by digital circuit designers in the current loop design include the consideration of the transmission of single-ended signals between two gate circuits (as shown in the figure below). The current loop from gate A to gate B, and then back to gate A from the ground plane.

There will be two potential problems in the picture above:

a. The ground plane between points A and B needs to be connected through a low-impedance path. If a large impedance is connected between the ground planes, there will be voltage backflow between the ground plane pins. This will inevitably lead to distortion of the signal amplitude of all devices and superimposition of input noise.

b. The area of the current return loop should be as small as possible. The loop is like an antenna. Generally speaking, a larger loop area will increase the chance of loop radiation and conduction. Every circuit designer hopes that the return current can be directly along the signal line, so that the smallest loop area.

Using large-area grounding can solve the above two problems at the same time. Large-area grounding can provide a small impedance between all grounding points, while allowing the return current to return as directly as possible along the signal line.

A common mistake among PCB designers is to make vias and slots in the ground plane. The figure below shows the direction of current flow when a signal line is on a slotted geoelectric layer. The loop current will be forced to bypass the slot, which will inevitably produce a large circulating loop.

Generally speaking, it is not possible to slot in the ground power plane. However, in some situations where slotting is inevitable, the PCB designer must first make sure that no signal loop passes through the slotted area. The same rules apply to mixed-signal circuits.

Unless multiple ground planes are used in the PCB board. Especially in the high-performance ADC circuit, the ground layer that separates the analog signal, digital signal and clock circuit can be used to effectively reduce the interference between signals. It needs to be emphasized again that in some occasions where slotting is inevitable, the PCB designer must first make sure that no signal loop passes through the slotted area.

In the power layer with a mirror difference, attention should also be paid to the area of the interlayer area (as shown in the figure below). At the edge of the board, there is the radiation effect of the power plane layer to the ground plane layer. Electromagnetic energy leaking from the edge will damage the adjacent boards. See figure a below. Properly reduce the area of the power plane layer (see figure b below), so that the ground plane layer overlaps in a certain area. This will reduce the impact of electromagnetic leakage on adjacent boards.

4. Signal wiring

The most important thing to ensure signal integrity is the physical wiring of the signal lines.PCB designers are often under working pressure, not only to complete the design in the shortest possible time, but also to ensure the integrity of the signal. Knowing how to balance the gap between possible problems and signals will promote the process of system design. High-speed current cannot effectively deal with discontinuities in signal lines. The problem of signal discontinuity is most likely to occur in the figure a below. In low-speed circuits, there is usually no need to consider signal discontinuity, but in high-speed circuits, this issue must be considered. Therefore, in the circuit design and using the method shown in b/c in the figure below, the continuity of the signal can be effectively guaranteed.

In high-speed circuit design, there is another common problem with signal wiring. If there is no special reason, all short wiring should be eliminated as much as possible. In high-frequency circuit design, short wiring is like radiation caused by impedance matching of signal lines.

Special attention should be paid to the routing of differential pairs in the routing of high-speed circuit design. The differential pair is driven by two fully complementary signal lines. The differential pair can avoid noise interference and improve the S/N rate. However, the differential pair signal line has particularly high requirements for wiring:

1. The two wires must be as close as possible to the wiring;

2. The length of the two lines must be exactly the same;

How to properly route the differential pair signal lines between two devices that are not arranged together is a key issue.

In the above picture a, due to the inconsistency of the length of the two signal lines, there will be some uncertain risks. The correct wiring should take the way shown in Figure b above. The general rule in differential pair wiring is to keep the two signal lines equally spaced and close to each other.

5. Crosstalk

In PCB design, crosstalk is another issue worthy of attention. The following figure shows the crosstalk area and the associated electromagnetic area between three adjacent pairs of parallel signal lines in a PCB. When the interval between the signal lines is too small, the electromagnetic regions between the signal lines will affect each other, resulting in signal deterioration, which is crosstalk.

Crosstalk can be solved by increasing the signal line spacing. However,PCB designers are usually constrained by increasingly tight wiring space and narrow signal line spacing; because there are no more choices in the design, it is inevitable to introduce some crosstalk problems in the design. Obviously, PCB designers need to be able to manage crosstalk problems. Many relevant rules for reliable spacing have been published over the years. A generally recognized rule in the industry is the 3W rule, that is, the distance between adjacent signal lines should be at least 3 times the width of the signal line. However, the acceptable signal line spacing in practice depends on factors such as actual application, working environment, and design redundancy. The signal line spacing changes from one situation to another and is calculated every time. Therefore, when crosstalk problems are unavoidable, crosstalk should be quantified. This can be represented by computer simulation technology. Using the simulator, the designer can determine the signal integrity effect and *estimate the crosstalk effect of the system.

6. Power decoupling

Power decoupling is now a standard practice in digital circuit design. Mentioning it here will help reduce noise problems on power lines. A clean power supply is essential to design a high-performance circuit. The high frequency noise superimposed on the power supply will cause problems for each adjacent digital device. Typical noise comes from ground bounces, signal radiation, or digital devices themselves. The easiest way to solve power supply noise is to use capacitors to decouple high-frequency noise on the ground. The ideal decoupling capacitor provides a low-impedance path to ground for high-frequency noise, thereby eliminating power supply noise. Choose decoupling capacitors based on actual applications. Most designers will choose surface mount capacitors as close as possible to the power supply pins, and the capacitance value should be large enough to provide a low-resistance path to ground for predictable power supply noise. The problem usually encountered when using decoupling capacitors is that decoupling capacitors cannot be simply regarded as capacitors. There are several situations:

a. Capacitor packaging will cause parasitic inductance;

b. Capacitors will bring some equivalent resistances;

c. The wire between the power supply pin and the decoupling capacitor will bring some equivalent inductance;

d. The wire between the ground pin and the ground plane will bring some equivalent inductance; the effect caused by this:

a. Capacitors will cause resonance effects on specific frequencies and the resulting network impedance will have a greater impact on signals in adjacent frequency bands;

b. The equivalent resistance (ESR) will also affect the low-resistance path formed by the decoupling of high-speed noise;

The following summarizes the effect this has on a digital designer:

a. The leads drawn from the Vcc and GND pins on the device need to be treated as small inductors. Therefore, it is recommended to make the Vcc and GND leads as short and thick as possible in the design.

b. Choose a capacitor with low ESR effect, which helps to improve the decoupling of the power supply;

c. Choosing small package capacitors will reduce package inductance. Changing the device with a smaller package will result in a change in temperature characteristics. Therefore, after selecting a small package capacitor, the layout of the device in the design needs to be adjusted.

In the design, replacing X7R capacitors with Y5V capacitors can ensure a smaller package and lower equivalent inductance, but at the same time it will also cost more device costs to ensure high temperature characteristics.

In the design, the decoupling of low-frequency noise with large-capacity capacitors should also be considered. Using separate electrolytic capacitors and tantalum capacitors can improve the cost-effectiveness of the device.

7. Summary:

Signal integrity is one of the most important issues throughout the design of high-speed digital circuits; here are some suggestions for ensuring signal integrity in digital circuit design:

a. Physically isolate sensitive components from noise components;

b. Impedance control, reflection and signal terminal matching;

c. Use continuous power and ground plane layers;

d. Try to avoid using right angles in wiring;

e. The wiring length of the differential pair is equal;

f. Crosstalk should be considered in the design of high-speed circuits;

g. Power supply decoupling problem;

A good grasp of the problems in digital circuit design mentioned above can help digital circuit designers find as many potential problems in circuit design as possible in the early stage of circuit design.