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PCB Tech

PCB Tech

PCB Tech

PCB Tech

Get PCB signal integrity, only 9 steps
2021-09-09
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Author:Frank



  
Signal integrity (Signal Inte grity, SI) refers to the quality of the signal on the signal line, that is, the ability of the signal to respond with the correct timing and voltage in the circuit. If the signal in the circuit can reach the receiver with the required timing, duration, and voltage amplitude, it can be determined that the circuit has good signal integrity. Conversely, when the signal cannot respond normally, a signal integrity problem occurs.


Signal integrity problems can cause or directly cause signal distortion, timing errors, incorrect data, address, control lines, and system errors, and even crash the system. This has become a very noteworthy problem in high-speed product design. This article first introduces the problem of PCB signal integrity, then explains the steps of PCB signal integrity, and finally introduces how to ensure the signal integrity of PCB design.

PCB signal integrity issues include


PCB signal integrity problems mainly include signal reflection, crosstalk, signal delay, and timing errors.

  1. Reflection: When the signal is transmitted on the transmission line, when the characteristic impedance of the transmission line on the high-speed PCB does not match the source impedance or load impedance of the signal, the signal will reflect, causing the signal waveform to overshoot and undershoot. The ringing phenomenon. Overshoot (Overs hoot) refers to the first peak (or valley) of a signal transition, which is the effect of extra voltage above the power level or below the reference ground level;

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  Undershoot (Unders hoot) refers to the next valley (or peak) of a signal transition. Excessive overshoot voltage often impacts for a long time to cause damage to the device, undershoot reduces the noise margin, and ringing increases the time required for signal stabilization, thereby affecting system timing.

  2. Crosstalk: In PCB, crosstalk refers to the undesired noise interference caused by electromagnetic energy to adjacent transmission lines through mutual capacitance and mutual inductance coupling when the signal propagates on the transmission line. It is the electromagnetic field caused by different structures. Produced by the interaction in the same area. Mutual capacitance induces coupling current, which is called capacitive crosstalk; and mutual inductance induces coupling voltage, which is called inductive crosstalk. On the PCB, crosstalk is related to trace length, signal line spacing, and the condition of the reference ground plane.

  3. Signal delay and timing error: The signal is transmitted on the PCB wire at a limited speed, and the signal is sent from the driving end to the receiving end, during which there is a transmission delay. Excessive signal delay or signal delay mismatch may cause timing errors and confusion of logic device functions.

  The high-speed digital system design analysis of signal integrity analysis can not only effectively improve the performance of the product, but also shorten the product development cycle and reduce the development cost. With the development of digital systems in the direction of high speed and high density, it is very urgent and necessary to master this design tool.

  In the continuous improvement and improvement of the signal integrity analysis model and calculation analysis algorithm, the digital system design method using signal integrity for computer design and analysis will be widely and comprehensively applied.

PCB signal integrity steps

  1. Preparation before design

  Before the design begins, we must first think and determine the design strategy, so as to guide work such as the selection of components, process selection and circuit board production cost control. As far as SI is concerned, it is necessary to conduct research in advance to form planning or design guidelines to ensure that the design results do not have obvious SI problems, crosstalk or timing problems.

  2. The stacking of circuit boards

  Some project teams have great autonomy in determining the number of PCB layers, while others do not. Therefore, it is important to understand where you are.

  Other important questions include: What are the expected manufacturing tolerances? What is the expected insulation constant on the circuit board? What is the allowable error of line width and spacing? What is the allowable error of the thickness and spacing of the ground layer and signal layer? All these letters

Information can be used in the pre-wiring phase.

  Based on the above data, you can choose to cascade. Note that almost every PCB inserted into other circuit boards or backplanes has thickness requirements, and most circuit board manufacturers have fixed thickness requirements for the different types of layers they can manufacture, which will greatly restrict the number of final stacks . You might want to work closely with the manufacturer to define the number of cascades. Impedance control tools should be used to generate target impedance ranges for different layers, and the manufacturing tolerances provided by the manufacturer and the influence of adjacent wiring must be considered.

3. Crosstalk and impedance control

  Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal line. The coupling analysis of adjacent parallel signal lines may determine the "safe" or expected spacing (or parallel wiring length) between signal lines or between various types of signal lines.

  For example, if you want to limit the clock-to-data signal node crosstalk to less than 100mV, but keep the signal traces parallel, you can use calculations or simulations to find the minimum allowable spacing between signals on any given wiring layer. At the same time, if the design contains important impedance nodes (or clocks or dedicated high-speed memory architecture), you must place the wiring on one layer (or several layers) to get the desired impedance.

  4. Important high-speed nodes

  Delay and time skew are key factors that must be considered in clock routing. Because of the strict timing requirements, such nodes usually must use termination devices to achieve the best SI quality. These nodes should be determined in advance, and the time required to adjust component placement and wiring should be planned in order to adjust the signal integrity design indicators.