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PCB Tech

PCB Single chip system (SOC) design and processing
2021-09-12
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Author:Frank

With the development of VLSI process technology, chip scales are getting larger and larger, and millions of gate-level circuits can be integrated on a chip. The development of a variety of compatible process technologies can integrate very different types of devices on the same chip. It opens up a broad technological approach for system integration. Really called system-level chip integration, not only puts several digital logic circuits with complex functions on the same chip to make a complete single-chip digital system, but also includes other types of electronic functional devices on the chip. , Such as analog devices and dedicated memory, some applications may be expanded, including radio frequency devices and even MEMS. Usually the system-level chip should include digital systems and analog electronic devices on a single chip at least.

    A dedicated system is required. Therefore, the development of SOC design will play a pivotal role in the future integrated circuit design industry. This article discusses the design techniques and processing methods necessary for a single-chip system based on the characteristics of the system-level chip. Because the single-chip system-level chip design has greater advantages compared with multi-chip systems in terms of speed, power consumption, and cost. In addition, the specificity of the electronic system has different applications.

    1. Features of System-on-Chip

    It has the following characteristics: The system-level chip is a single chip to realize the integration of a full electronic system.

    1. Large scale and complex structure.

    And the circuit structure also includes MPUSRA MDRA MEPROM flash memory, ADCDA C and other analog and radio frequency circuits. In order to shorten the time to market, millions of gates or even hundreds of millions of components are designed. The design starting point is required to be higher than that of ordinary ASICs, and you cannot rely on basic logic and circuit units as basic units, but use larger components or modules called intellectual property IP. In the verification method, a mixed-signal verification method in which digital and analog circuits are combined should be adopted. In order to effectively test each module, especially IP, it is necessary to design for testability.

    2. High speed and close timing relationship.

    It brings many problems to the design, such as the system clock frequency up to hundreds of megabytes and the intricate timing relationships within and between modules. Such as timing verification, low-power design and high-frequency effects such as signal integrity, electromagnetic interference, and signal crosstalk.

    In the case of deep sub-micron, the trace delay becomes indispensable compared with the gate delay, and the deep sub-micron process technology is mostly used in system-level chips. And become the main factor. In addition, the complicated timing relationship of the system-level chip increases the difficulty of timing matching in the circuit. The very small line-to-line moment and layer spacing of the deep sub-micron process enhances the signal coupling between lines and layers. In addition to the very high system operating frequency, electromagnetic interference and signal crosstalk are aggravated, making design verification difficult.

    2. SOC design technology

    1 Design reuse

    It is not possible to design a system-on-chip with a scale of millions of gates from scratch. To build the design on a higher level. It is necessary to use more IP multiplexing technology. Only in this way can the design be completed quickly, ensure the success of the design, and obtain a low-cost SOC to meet market demand.

    For future design and utilization. Core cores are usually divided into three types. The design reuse is based on the core core (CORE), and various verified super macro cell module circuits are made into core cores. One is called a hard core, which is connected to a specific process. The physical layout of the system has been verified by the film test. It can be directly called by the new design as a specific functional module. The second is a soft core, written in hardware description language or C language, and used for functional simulation. The third is a solid The core (firmcore soft core) is developed on the basis of a comprehensive soft core with layout planning. At present, the design reuse method relies to a large extent on the solid core, which combines the RTL-level description with the specific standard cell library for logic Comprehensive optimization to form a gate-level netlist, and finally form the hard core required by the design through the layout tool. This soft RTL synthesis method provides some design flexibility, and can be combined with specific applications, appropriately modified description, and re-verified to meet Specific application requirements. In addition, with the development of process technology, the new library can also be used to re-synthesize, optimize, place and route, and re-verify to obtain hard cores under new process conditions. This method is used to achieve design reuse and traditional module design methods. The efficiency can be increased by 2-3 times. Therefore, the design reuse before the 0.35um process is mostly realized by this RTL soft core synthesis method.

    Deep sub-micron (DSM makes the system-on-chip larger and more complex. This comprehensive method will encounter new problems, with the development of process technology. Because as the process develops to 0.18um or smaller size, it is not necessary to accurately handle The gate delay is the interconnect delay. In addition to the hundreds of megabytes of clock frequency, the timing relationship between the signals is very strict, so it is difficult to use the soft RTL synthesis method to achieve the purpose of design and reuse. System-on-chip based on the core core Design shifts the design method from circuit design to system design. The focus of design will shift from today's logic synthesis, gate-level placement and routing, post-simulation to system-level simulation, software and hardware co-simulation, and physical design combining several cores. Forcing the design industry to polarize, one is to turn to the system, using IP to design high-performance and high-complex dedicated systems. The other is to design the core under the DSM and enter the physical layer design to make the performance of the DSM core better and more reliable. Met test.

    2. Low power design

    There will be tens of watts or even hundreds of watts of power consumption. Huge power consumption brings problems in terms of packaging and reliability. System-on-chips work at a clock frequency of hundreds of megabytes due to the integration of more than one million gates. Therefore, the design of reducing power consumption is an inevitable requirement of system-level chip design. In the design, we should start to reduce the power consumption of the chip from many aspects.

    Reducing the operating voltage is one aspect, the system design aspect. But too low operating voltage will affect system performance. The more mature method is to use idle mode (Idle mode and low power consumption mode). When there is no task, the system is in a waiting state or in a low power consumption mode with low voltage and low clock frequency. The use of programmable power supply is to obtain high performance and low power consumption. An effective method of energy consumption.

    Because the complementary circuit structure has a pair of PNMOS transistors at each gate input, the traditional complementary circuit structure is used as little as possible in the circuit configuration structure. A large capacitive load is formed. When the CMOS circuit is working, the power consumption of charging and discharging the load capacitance switch accounts for more than 70% of the total power consumption. Therefore, the circuit structure configuration of deep submicron is mostly selected for the circuit structure group with low load capacitance. State, such as switch logic, Domino logic and NP logic, make the speed and power consumption better optimized.

    A system with a frequency of hundreds of megabytes can't work everywhere with a frequency of hundreds of megabytes, and a low-power logic design. Low-power gates can be used for those parts of the circuit where the speed is not high or the driving capability is not large, so as to reduce the power consumption of the system. Therefore, the low-power optimization design is added in the logic synthesis, and the unit circuit with low power consumption is used as much as possible under the prerequisite of meeting the working speed of the circuit.

    Almost all MOS output circuits use a pair of complementary P and NMOS tubes, and use low-power circuit design techniques. During the switching process, two devices are turned on at the same time, which causes a lot of power consumption. There are many legs to the system-level chip and the circuit frequency is high. This phenomenon is even more serious. Therefore, this problem should be avoided as much as possible in the circuit design. Appear to reduce power consumption.

    2. Testability design technology

    The core is buried deep in the chip. The system-level chip integrates the core and user-defined logic (UDL). The core cannot be tested in advance. It can only be used as a part of the system-level chip after the system-level chip is manufactured. Tests on chips and chips at the same time. Therefore, there are many difficulties in system-level chip testing. First of all, the core is someone else’s choice. The designer of the core may not have a good understanding of the core, and does not have the knowledge and ability to test the core. The core is buried deep in the chip, and the integrated core test cannot be processed by the method of testing a single independent core. The core and the peripheral test resources can only be connected through the access of a certain circuit module, a common method There are the following:

    Connect the I/O end of the core directly to the lead-out end of the chip, 1 parallel direct access technology. Or the core I/O terminal and the chip lead terminal are shared by a multiplexer. This method is often used for chips with fewer cores clamped into the chip or chips with abundant terminals available. The advantage of parallel direct access is that it can directly use the independent core test method to test the clamped core on the chip.

    This method is to set up a scan chain around the core, 2 serial scan link entry method. All the I/O of the core can be connected to the periphery indirectly. Through the scan chain, the test pattern can be transmitted to the test point, and the test response result can also be transmitted. Boundary scan technology is a specific access method. The advantage of the serial scanning method is that it saves lead-out ports. 3 access to the functional testing organization, this method is to access the logic module around the core to generate or disseminate test patterns. On-chip self-testing is one of them. On-chip access to test resources is used to test specific cores. The self-test reduces the complexity of the peripheral access module, and only a simple test interface is required. This method can be used for most memory tests, and the self-test logic and the memory core are designed together.

    To ensure that each core is correct. Cross-core tests should also be carried out through the surrounding logic circuits. A complete system-level chip test should include the core core internal tests. As well as testing of user-defined logic circuits. The task of testability design during chip design is to connect the test device and the system-level circuit under test into a unified mechanism through the DFT test circuit. The access path of each core can be connected to the main I/O end of the chip via the multiplexer, the test access path can be connected to the chip bus, or the test points that need to be controlled and observed can be connected to the scan Chain. Form a unified whole that can be controlled by the test device.

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    4 Physical synthesis of deep submicron SOC

    The delay depends on the physical layout. Therefore, the traditional top-down design method only knows the delay after completing the physical layout. If timing errors are discovered at this time, the main delay factor is the interconnect delay due to the deep sub-micron time. Must return to the front end, modify the front-end design or re-layout, this kind of repetitive design from placement and routing to re-synthesis may have to be performed many times to achieve the timing goal. As the feature size decreases, the influence of interconnection lines becomes greater and greater. The traditional design method of logic synthesis and separate placement and routing has become unable to meet the design requirements. The logic synthesis and layout must be more closely linked, and physical synthesis methods are used to enable designers to consider both high-level functional issues, structural issues, and low-level layout issues at the same time. The physical synthesis process is divided into three stages: initial planning, RTL planning and gate-level planning. In the initial planning stage, first complete the initial layout, place the RTL module on the chip, and complete the I/O layout and power line planning. According to the circuit timing analysis and the wiring congestion degree analysis, the designer can re-divide the circuit module. Through the top-level wiring, the wiring between the modules is carried out. And extract the parasitic parameters, generate an accurate wire network model, determine the timing constraints of each RTL module, and form a comprehensive constraint.

    Then carry out the quick layout to get a more accurate description of the RTL module. And based on this description, the layout of the top-level wiring and pin positions are fine-tuned. Finally, the line load model of each RTL module and the precise comprehensive constraints of each module are obtained. The RTL planning stage is to estimate the area and timing of the RTL module more accurately. Quickly survive the gate-level netlist through the RTL estimator. Complete the gate-level netlist, and the gate-level planning is to independently comprehensively optimize each RTL-level module. Finally, place and route. Synthesize a clock tree for each RTL module and the entire chip. It also performs timing and line congestion analysis, and if problems are found, local modifications can be made. Since the physical synthesis process is closely connected with the front-end logic synthesis, and the logic synthesis is carried out on the basis of placement and routing, the delay model is accurate and the design iterations are less.

    5. Design verification technology

    The larger the circuit scale, the more complex the system, the longer the verification time will be. At present, there are CAD tools suitable for different design fields and design objects on the market. However, if these tools are used to verify the system-level chip design, it needs to be combined. Design verification is a very important part of the design work. And integrated in the same environment.

    Most simulation tools are derived from SPICE, and analog circuit simulation requires transistor-level models. Due to the need to solve circuit equations, the more complex the circuit, the longer the simulation time. The parallel structure is used for numerical calculation and the model is used for simulation, which can greatly increase the simulation speed, and can simulate tens of thousands of device circuits and even cores. However, it is still difficult to simulate the entire SOC with a scale of millions of gates. On the other hand, the deep submicron system-level chip line network delay exceeds the gate delay, and the operating frequency is hundreds of megabytes. Interference between signals and signal integrity analysis are also necessary. It can be determined by transistor-level simulation. The digital signal simulation only needs logic model, the simulation speed is fast, and the scale is large. From this point of view, after physical design, the transistors and wiring parameters of each module are extracted, and module-level verification is performed first. On this basis, joint simulations with simulators supporting multiple different models are used to solve verification problems in SOC design.

    Almost all microprocessors and specialized software and hardware are used. The hardware and software are closely related, but before the system is made, it is on the system-level chip. The interaction between software and hardware is usually difficult to accurately detect some design errors and will not be obvious. In order to solve this problem, hardware/software co-verification technology must be adopted.

    3. Silicon processing technology is a key factor for the success of monolithic system design

    It is also necessary to decide what processing technology to use. The CMOS digital logic processing capabilities of various ASIC manufacturers are not very different. When designing a system-level chip, apart from choosing design tools, cell libraries and cores. But for monolithic system integration, Lei said, other special modules must be added as needed, which requires additional mask process steps. For example, SRA M needs to add two masks, for flash memory, it needs to add 5 masks, for analog circuits, it needs to add at least 2-3 masks for metal-metal capacitors, polycrystalline-polycrystalline capacitors and Production of polysilicon resistors. There is a big difference for these different manufacturers. The designer must follow the special module requirements and IP core requirements to select a suitable processing manufacturer, so that the process can meet the core core indicators and special module requirements. If you plan to make a mixed-signal monolithic system, you must choose a manufacturer to deal with the isolation between analog module processing capabilities and digital/analog enough to meet the monolithic system design requirements.