PCB Tech - PCB design skills 10 tips to share

PCB design skills 10 tips to share
1. How to avoid crosstalk in PCB design?
A changed signal (such as a step signal) propagates along the transmission line from A to B. A coupled signal will be generated on the transmission line CD. Once the changed signal ends, that is, when the signal returns to a stable DC level, the coupled signal will not exist, so crosstalk It only occurs in the process of signal hopping, China IC37 network and the faster the signal edge changes (conversion rate), the greater the crosstalk generated. The electromagnetic field coupled in the space can be extracted as a collection of countless coupling capacitors and coupling inductances. The crosstalk signal generated by the coupling capacitor can be divided into forward crosstalk and reverse crosstalk Sc on the victim network. These two signals have the same polarity; The crosstalk signal generated by the inductance is also divided into forward crosstalk and reverse crosstalk SL, and these two signals have opposite polarities. The forward crosstalk and reverse crosstalk generated by the coupled inductance and capacitance exist at the same time and are almost equal in size. In this way, the forward crosstalk signals on the victim network cancel each other due to the opposite polarity, and the reverse crosstalk polarity is the same, and the superposition is enhanced. The modes of crosstalk analysis usually include default mode, three-state mode and worst-case mode analysis of China ICPDF network. The default mode is similar to the way we actually test the crosstalk, that is, the offending network driver is driven by a flip signal, and the victim network driver maintains the initial state (high level or low level), and then the crosstalk value is calculated. This method is more effective for crosstalk analysis of unidirectional signals. The tri-state mode means that the driver of the offending network is driven by a flip signal, and the tri-state terminal of the victim network is set to a high-impedance state to detect the size of the crosstalk. This method is more effective for two-way or complex topology networks. The worst-case analysis refers to keeping the driver of the victim network in the initial state, and the simulator calculates the sum of the crosstalk of all the default infringement networks to each victim network. This method generally only analyzes individual key networks, because there are too many combinations to be calculated and the simulation speed is relatively slow.

2. Is there any regulation on the copper area of the conduction band, that is, the ground plane of the microstrip line?
For microwave circuit design, the area of the ground plane has an impact on the parameters of the transmission line. The specific algorithm is more complicated (please refer to the relevant information of EESOFT by Angelen). In general PCB digital circuit transmission line simulation calculations, the ground plane area has no effect on the transmission line parameters, or ignores the impact.
3. In the emc test, it was found that the harmonics of the clock signal exceeded the standard very seriously, but the decoupling capacitor was connected to the power supply pin. What aspects should be paid attention to in PCB design to suppress electromagnetic radiation?
The three elements of EMC are radiation source, transmission route and victim. The propagation path is divided into space radiation propagation and cable conduction. So to suppress harmonics, first look at the way it spreads. Power supply decoupling is to solve the propagation of conduction mode. In addition, necessary matching and shielding are also required.
4. Among the products with 4-layer board design, why some are double-sided paving, and some are not?
There are several considerations for the role of paving: 1. Shielding; 2. Heat dissipation; 3. Reinforcement; 4. PCB process requirements. So no matter how many layers of slabs are laid, we must first look at the main reasons. Here we mainly discuss high-speed issues, so we mainly talk about shielding. Surface paving is good for EMC, but copper paving should be as complete as possible to avoid islands. Generally, if there are many surface-layer device wiring, it is difficult to ensure the integrity of the copper foil, and it will also cause the problem of inter-segmentation of the inner layer signal. Therefore, it is recommended not to lay copper on the surface-layer devices or boards with many traces.
5. For a group of buses (address, data, command) driving multiple (up to 4, 5) devices (FLASH, SDRAM, other peripherals...), which method is used when PCB wiring?
The influence of wiring topology on signal integrity is mainly reflected in the inconsistent signal arrival time on each node, and the reflected signal also does not arrive at a certain node in the same time, which causes the signal quality to deteriorate. Generally speaking, in a star topology, you can control several stubs of the same length to make the signal transmission and reflection delays consistent to achieve better signal quality. Before using the topology, it is necessary to consider the situation of the signal topology node, the actual working principle and the wiring difficulty. Different buffers have inconsistent effects on signal reflection, so the star topology cannot solve the delay of the data address bus connecting to flash and sdram, and thus cannot ensure the quality of the signal; on the other hand, high-speed signals generally For communication between dsp and sdram, the speed of flash loading is not high, so in high-speed simulation, you only need to ensure the waveform at the node where the actual high-speed signal works effectively, instead of paying attention to the waveform at the flash; star topology is compared with daisy chain and other topologies. In other words, wiring is more difficult, especially when a large number of data address signals use star topology. The attached figure is the simulation waveform of using Hyperlynx simulation data signal in DDR--DSP--FLASH topology connection, and DDR--FLASH--DSP connection at 150MHz. It can be seen that in the second case, the signal quality at the DSP is better, but the waveform at the FLASH is worse, and the actual working signal is the waveform at the DSP and DDR.
6. For PCB with frequency above 30M, use automatic wiring or manual wiring when wiring; are the software functions of wiring the same?
Whether the high-speed signal is based on the rising edge of the signal rather than the absolute frequency or speed. Automatic or manual wiring depends on the support of the software wiring function. Some wiring may be better than automatic wiring manually, but for some wiring, such as checking distribution lines, bus delay compensation wiring, the effect and efficiency of automatic wiring will be much higher than manual wiring. Generally, the substrate of PCB copy board is mainly composed of a mixture of resin and glass cloth. Due to the different proportions, the dielectric constant and thickness are different. Generally, the higher the resin content, the smaller the dielectric constant, the thinner it can be. For specific parameters, please consult the PCB manufacturer. In addition, with the emergence of new processes, there are also PCB boards of some special materials that are provided for such as ultra-thick backplanes or low-loss RF boards.
7. In PCB design, the ground wire is usually divided into protective ground and signal ground; the power ground is divided into digital ground and analog ground. Why should the ground wire be divided?
The purpose of dividing the ground is mainly for EMC considerations, and it is worried that the noise on the digital part of the power supply and the ground will interfere with other signals, especially analog signals through the conduction path. As for the division of signal and protective ground, it is because the consideration of ESD static discharge in EMC is similar to the role of lightning rod grounding in our lives. No matter how you divide it, there is only one land in the end. It's just that the noise emission method is different. 8. Is it necessary to add ground wire shields on both sides when fabricating the clock?
Whether to add a shielded ground wire or not depends on the crosstalk/EMI situation on the board, and if the shielded ground wire is not handled well, it may make the situation worse.
9. What are the corresponding countermeasures when deploying clock lines of different frequencies? For the wiring of the clock line, it is best to perform signal integrity analysis, formulate corresponding wiring rules, and perform wiring according to these rules. 10. When the PCB single-layer board is manually wired, should it be placed on the top layer or the bottom layer? If the device is placed on the top layer, the bottom layer is routed.