PCB Tech - PCB layout and installation of decoupling capacitors

The formation of spike current:

The magnitude of the current drawn from the power supply when the digital circuit outputs high level is generally different from the current injected during low-level output, that is, the current sinked during low-level output>the current drawn by the power supply.

The waveform of the peak power supply current varies with the type of device used and the capacitive load connected to the output terminal.

The main reasons for the spike current are:

The T3 and T4 tubes of the output stage are turned on at the same time in the short design. In the process of the NAND gate from output low level to high level, the negative jump of the input voltage produces a large reverse drive current in the base loop of T2 and T3, because the saturation depth of T3 is designed to be greater than that of T2 Large, the reverse drive current will cause T2 to escape from saturation first and cut off. After T2 is turned off, its collector potential rises, turning on T4. But at this time T3 has not been out of saturation, so in a very short design, T3 and T4 will be turned on at the same time, thereby generating a large ic4, causing the power supply current to form a peak current. R4 in the figure is designed to limit this peak current.

R4 in the low-power TTL gate circuit is larger, so its peak current is smaller. When the input voltage changes from low to high, the output level of the NAND gate changes from high to low. At this time, T3 and T4 may also be turned on at the same time. But when T3 starts to be turned on, T4 is in amplifying state, and the voltage between the collector and emitter of the two tubes is larger, so the peak current generated is smaller, and the impact on the power supply current is relatively small.

Another cause of spike current is the influence of load capacitance. There is actually a load capacitor CL at the output of the NAND gate. When the output of the gate changes from low to high, the power supply voltage is charged by T4 to the capacitor CL, thus forming a spike current.

When the output of the NAND gate changes from high level to low level, the capacitor CL discharges through T3. At this time, the discharge current does not pass through the power supply, so the discharge current of CL has no effect on the power supply current.

Suppression method of spike current:

1. Take measures on the wiring of the circuit board to minimize the stray capacitance of the signal line;

2. Another method is to try to reduce the internal resistance of the power supply so that the peak current will not cause excessive power supply voltage fluctuations;

3. The usual practice is to use decoupling capacitors for filtering, usually placed at the power inlet of the circuit board.

A 1uF～10uF decoupling capacitor to filter out low-frequency noise; a 0.01uF～0.1uF decoupling capacitor (high-frequency filter capacitor) is placed between the power and ground of each active device in the circuit board. Filter out high frequency noise. The purpose of filtering is to filter out the AC interference superimposed on the power supply, but it is not that the larger the capacitance of the capacitor used, the better, because the actual capacitor is not an ideal capacitor and does not have all the characteristics of an ideal capacitor.

The selection of the decoupling capacitor can be calculated according to C=1/F, where F is the circuit frequency, that is, 0.1uF for 10MHz and 0.01uF for 100MHz. Generally, it can be 0.1~0.01uF.

The high-frequency filter capacitor placed next to the active device has two functions. One is to filter out high-frequency interference conducted along the power supply, and the other is to timely supplement the peak current required for high-speed operation of the device. So the placement of the capacitor needs to be considered.

Due to the parasitic parameters of the actual capacitor, it can be equivalent to the resistance and inductance connected in series on the capacitor, which are called equivalent series resistance (ESR) and equivalent series inductance (ESL). In this way, the actual capacitor is a series resonant circuit.

The actual capacitor is capacitive at frequencies lower than Fr, and inductive at frequencies higher than Fr, so the capacitor is more like a band-stop filter.

The 10uF electrolytic capacitor has a large ESL and Fr less than 1MHz, which has a better filtering effect on low-frequency noise such as 50Hz, but has no effect on high-frequency switching noise of hundreds of megabytes.

The ESR and ESL of a capacitor are determined by the structure of the capacitor and the medium used, rather than the capacitance. The ability to suppress high-frequency interference cannot be improved by using a larger capacity capacitor. For the same type of capacitor, at a frequency lower than Fr, the impedance of the larger capacity is smaller than that of the smaller capacity, but if the frequency is higher than Fr, ESL determines There will be no difference in impedance between the two.

Using too many large-capacity capacitors on the circuit board is not helpful for filtering high-frequency interference, especially when using high-frequency switching power supplies. Another problem is that too many large-capacity capacitors increase the impact on the power supply when powering on and hot-swapping the circuit board, which is likely to cause problems such as power supply voltage drop, circuit board connector ignition, and slow voltage rise in the circuit board.

Placement of decoupling capacitors in PCB layout

For the installation of capacitors, the first thing to mention is the installation distance. The capacitor with the smallest capacitance has the highest resonant frequency and the smallest decoupling radius, so it is placed closest to the chip. The larger capacity can be farther away, and the outermost layer has the largest capacity. However, all capacitors that decouple the chip should be as close as possible to the chip.

Another point to note is that when placing it, it is best to distribute it evenly around the chip, and this must be done for each capacitance level. Usually the arrangement of the power and ground pins is taken into account when the chip is designed, and they are generally evenly distributed on the four sides of the chip. Therefore, voltage disturbances exist all around the chip, and the decoupling must also decouple the entire chip area evenly. If the 680pF capacitors in the above figure are all placed on the upper part of the chip, due to the decoupling radius problem, then the voltage disturbance at the lower part of the chip cannot be well decoupled.

Capacitor installation

When installing the capacitor, pull out a short lead wire from the pad, and then connect it to the power plane through the via hole, and the same is true for the ground terminal. In this way, the current loop flowing through the capacitor is: power plane-vias-lead wires-pads-capacitors-pads-lead wires-vias-ground plane, the following figure intuitively shows the current的reflux path.

The first method leads out a long lead wire from the pad and then connects to the via hole. This will introduce a large parasitic inductance. This must be avoided. This is the worst installation method.

The second method drills holes at the two ends of the pad next to the pad, which has a much smaller road area than the first method, and the parasitic inductance is also small, which is acceptable.

The third type is to drill holes on the side of the pad, which further reduces the loop area, and the parasitic inductance is smaller than the second type, which is a better method.

The fourth method has holes on both sides of the pad. Compared with the third method, it is equivalent to that each end of the capacitor is connected to the power plane and the ground plane in parallel through vias, which is smaller than the third parasitic inductance. Space permits, try to use this method.

The last method is to directly drill holes on the pads, with the least parasitic inductance, but welding may cause problems. Whether to use it depends on the processing ability and method.

The third and fourth methods are recommended.

It needs to be emphasized that some PCB engineers sometimes use common vias for multiple capacitors in order to save space. Do not do this under any circumstances. It is best to find a way to optimize the design of the capacitor combination and reduce the number of capacitors.

Since the wider the printed line, the smaller the inductance, the lead-out line from the pad to the via should be as wide as possible, and if possible, try to be the same width as the pad. In this way, even if it is a capacitor in a 0402 package, you can also use a 20mil-wide lead wire.