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PCB Tech

PCB Tech - How to enhance ESD function in PCB design

PCB Tech

PCB Tech - How to enhance ESD function in PCB design

How to enhance ESD function in PCB design

2021-10-16
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Author:Downs

In the PCB design, the anti-ESD design of the PCB can be achieved through layering, proper layout and installation. In the design process, the vast majority of design modifications can be limited to the addition or reduction of components through prediction. By adjusting the PCB layout and routing, ESD can be well prevented.

Static electricity from the human body, the environment, and even electronic equipment can cause various damages to precision semiconductor chips, such as penetrating the thin insulating layer inside the components; destroying the gates of MOSFET and CMOS components; and the triggers in CMOS devices are locked ; Short-circuit reverse-biased PN junction; Short-circuit forward-biased PN junction; Melt the welding wire or aluminum wire inside the active device. In order to eliminate electrostatic discharge (ESD) interference and damage to electronic equipment, a variety of technical measures need to be taken to prevent it.

In the design of the PCB board, the anti-ESD design of the PCB can be realized through layering, proper layout and installation. In the design process, the vast majority of design modifications can be limited to the addition or reduction of components through prediction. By adjusting the PCB layout and routing, ESD can be well prevented. The following are some common precautions.

pcb board

Use multi-layer PCB s as much as possible. Compared with double-sided PCBs, the ground plane and power plane, as well as the tightly arranged signal line-ground spacing can reduce the common mode impedance and inductive coupling, making it 1/of the double-sided PCB. 10 to 1/100. Try to put each signal layer close to a power layer or ground layer as much as possible. For high-density PCBs with components on the top and bottom surfaces, short connection lines, and many filling grounds, you can consider using inner layer lines.

For double-sided PCBs, tightly interwoven power and ground grids are used. The power line is close to the ground line, and as many connections as possible between the vertical and horizontal lines or the filled area. The grid size on one side is less than or equal to 60mm. If possible, the grid size should be less than 13mm.

to ensure that each circuit is as compact as possible.

Put all the connectors aside as much as possible.

If possible, lead the power cord from the center of the card and keep it away from areas that are directly affected by ESD.

On all PCB layers below the connector that leads to the outside of the chassis (which is easily directly hit by ESD), place a wide chassis ground or a polygonal fill ground, and connect them together with vias at a distance of about 13mm.

Place mounting holes on the edge of the card, and connect the top and bottom pads with no solder resist around the mounting holes to the chassis ground.

During PCB assembly, do not apply any solder on the top or bottom pads. Use screws with built-in washers to achieve close contact between the PCB and the metal chassis/shielding layer or the support on the ground plane.

The same "isolation zone" should be set between the chassis ground and circuit ground of each layer; if possible, keep the separation distance of 0.64mm.

At the top and bottom layers of the card near the mounting holes, connect the chassis ground and the circuit ground with a 1.27mm wide wire every 100mm along the chassis ground. Adjacent to these connection points, place pads or mounting holes for mounting between the chassis ground and the circuit ground. These ground connections can be cut with a blade to keep the circuit open, or jumper with magnetic beads/high-frequency capacitors.

If the PCB circuit board will not be placed in a metal chassis or shielding device, solder resist should not be applied to the top and bottom chassis ground wires of the circuit board, so that they can be used as discharge electrodes for ESD arcs.