Ultra-precision PCB Fabrication, High Frequency PCB, High Speed PCB, IC Substrate, Multilayer PCB and PCB Assembly.
The most reliable PCB custom service factory.
PCB Tech

PCB Tech

PCB Tech

PCB Tech

How to avoid the negative effect of vias in high speed PCB design

1、 Basic concept of via hole

Via is one of the most important parts of Multilayer PCB. The cost of drilling usually accounts for 30% to 40% of the cost of PCB production. In short, every hole on a PCB can be called a via. In terms of function, vias can be divided into two types: one is used for electrical connection between layers; the other is for fixing or positioning devices. In terms of process, these vias are generally divided into three categories: blind via, buried via and through via. The blind hole is located on the top and bottom surface of printed circuit board, and has a certain depth. It is used to connect the surface circuit and the inner circuit below. The depth of the hole is usually not more than a certain ratio (aperture). Buried hole refers to the connecting hole in the inner layer of printed circuit board, which does not extend to the surface of the circuit board. The above two types of holes are located in the inner layer of PCB. Before lamination, the through-hole molding process is used to complete the process, and several inner layers may be overlapped in the process of via forming.

The third type is called through hole, which passes through the whole circuit board and can be used for internal interconnection or as the installation positioning hole of components. Because the through-hole is easier to realize and the cost is lower, most printed circuit boards use it instead of the other two. The vias mentioned below, without special instructions, are considered as through-holes.

From the design point of view, a through hole is mainly composed of two parts, one is the middle drill hole, the other is the pad area around the drill hole. The size of these two parts determines the size of the via. Obviously, in high-speed, high-density PCB design, designers always hope that the smaller the via, the better, so that there can be more wiring space on the board. In addition, the smaller the via, the smaller its own parasitic capacitance is, which is more suitable for high-speed circuits. However, the decrease of hole size brings the increase of cost, and the size of through-hole can not be reduced without limit. It is limited by drilling and plating technology: the smaller the hole is, the longer the drilling time is, and the easier it is to deviate from the center position. Moreover, when the depth of the hole is more than 6 times of the diameter of the hole, it is impossible to guarantee the uniform copper plating on the hole wall. For example, if the thickness (through-hole depth) of a normal 6-layer PCB is 50 Mil, under normal conditions, the diameter of drilling hole provided by PCB manufacturer can only reach 8 mil. With the development of laser drilling technology, the size of drilling hole can also be smaller and smaller. Generally, through hole with diameter less than or equal to 6mils is called micropore. Micropores are often used in HDI (high density interconnection structure) design. Microporous technology allows vias to be directly punched on the pad, which greatly improves the circuit performance and saves wiring space.

high speed PCB design

high speed PCB design

Vias are discontinuous impedance breakpoints on transmission lines, which can cause signal reflection. In general, the equivalent impedance of vias is about 12% lower than that of transmission lines. For example, the impedance of 50 ohm transmission lines will decrease by 6 ohm when passing through vias (it is related to the size of vias and the thickness of plates, but not the reduction). But the reflection caused by the impedance discontinuity of via is actually very small, and its reflection coefficient is only (44-50) / (44 + 50) = 0.06, and the problems caused by via mainly focus on the influence of parasitic capacitance and inductance.

2、 Parasitic capacitance and inductance of via

If the diameter of solder mask area of via is D2, the diameter of via pad is D1, the thickness of PCB is t, and the dielectric constant of substrate is ε, the parasitic capacitance of via is approximately C = 1.41 ε TD1 / (d2-d1)

The main influence of the parasitic capacitance of via on the circuit is to extend the rising time of the signal and reduce the speed of the circuit. For example, for a PCB with a thickness of 50mil, if the via pad diameter is 20MIL (drilling diameter is 10mils), and the solder mask diameter is 40mil, Then we can approximately calculate the parasitic capacitance of the via by the above formula: C = 1.41x4.4x0.050x0.020 / (0.040-0.020) = 0.31pf. The rise time variation caused by this capacitance is: t10-90 = 2.2c (Z0 / 2) = 2.2x0.31x (50 / 2) = 17.05ps

From these values, it can be seen that although the effect of the parasitic capacitance of a single via is not obvious, if the vias are used repeatedly for layer switching in the wiring, multiple vias will be used, which should be carefully considered in the design. In the actual design, the parasitic capacitance can be reduced by increasing the distance between via and copper layer (anti pad) or decreasing the diameter of pad.

In the design of high-speed digital circuit, the harm caused by parasitic inductance of via is often greater than that of parasitic capacitance. Its parasitic series inductance will weaken the contribution of bypass capacitance and the filtering efficiency of the whole power system. We can use the following empirical formula to simply calculate the parasitic inductance of a via: l = 5.08h [ln (4h / D) + 1], where l is the inductance of the via, h is the length of the via, and D is the diameter of the central hole. It can be seen from the formula that the diameter of the via has little effect on the inductance, while the length of the via hole has an effect on the inductance. Still using the above example, we can calculate the via inductance as follows: l = 5.08x0.050 [ln (4x0.050 / 0.010) + 1] = 1.015nh. If the rise time of the signal is 1ns, then its equivalent impedance is: XL = π L / t10-90 = 3.19 Ω. This impedance can not be ignored when there is a high frequency current passing through. It should be noted that the bypass capacitance needs to pass through two vias when connecting the power layer and the stratum, so the parasitic inductance of the via will be doubled.

3、 How to use vias

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to the circuit design. In order to reduce the adverse effects caused by the parasitic effect of vias, we can try our best to do the following in the design:

1. From the two aspects of cost and signal quality, choose a reasonable size of via size. If necessary, vias of different sizes can be considered. For example, for vias of power supply or ground wire, larger sizes can be used to reduce impedance, while smaller vias can be used for signal wiring. Of course, with the decrease of via size, the corresponding cost will also increase.

2. From the two formulas discussed above, it can be concluded that the use of thinner PCB is beneficial to reduce the two parasitic parameters of via.

3. Try not to change the layer of the signal wiring on the PCB board, that is to say, try not to use unnecessary via.

4. The pin of power supply and ground should be drilled nearby, and the shorter the lead between the via and the pin, the better. In order to reduce the equivalent inductance, multiple vias in parallel can be considered.

5. Place some grounded vias near the vias of signal layer change, so as to provide close loop for signals. Some redundant grounding vias can even be placed on the PCB board.

6. For high-speed PCB with high density, micro via can be considered.