PCB Tech - IC packaging terminology for PCB copy board

For the general PCB copying engineer, it is necessary to have a certain understanding of IC packaging on the PCB circuit board when it is difficult to identify the circuit board copying board and the packaged device analysis, especially for some technology that initially involves PCB copying. Personnel, unfamiliar with certain professional terms may affect the technical analysis of the circuit board and the process of PCB copying. Here, we will introduce in detail the relevant industry terminology about IC packaging technology on PCB for reference and learning by PCB copy board or PCB design engineers.

1. BGA (ball grid array)

A display of spherical contacts, one of the surface mount packages. On the back of the printed circuit board, spherical bumps are produced in the display mode to replace the pins, and the LSI chip is assembled on the front side of the printed circuit board, and then sealed by molding resin or potting. Also called bump display carrier (PAC). Pins can exceed 200, which is a package for multi-pin LSI. The package body can also be made smaller than QFP (Quad Flat Package). For example, a 360-pin BGA with a pin center distance of 1.5mm is only 31mm square; while a 304-pin QFP with a pin center distance of 0.5mm is 40mm square. And BGA does not have to worry about pin deformation like QFP. This package was developed by Motorola Corporation of the United States. It was first adopted in portable phones and other devices, and may be popularized in personal computers in the United States in the future. Initially, the BGA pin (bump) center distance was 1.5mm, and the number of pins was 225. There are also some LSI manufacturers that are developing 500-pin BGAs. The problem with BGA is the visual inspection after reflow soldering. It is not yet clear whether an effective visual inspection method is available. Some believe that due to the large center distance of welding, the connection can be regarded as stable and can only be processed through functional inspection. The American Motorola company calls the package sealed with molded resin OMPAC, and the package sealed by the potting method is called GPAC (see OMPAC and GPAC).

2. BQFP (quad flat package with bumper)

Four-side pin flat package with cushion. One of the QFP packages, bumps (buffer pads) are provided at the four corners of the package body to prevent the pins from bending and deforming during transportation. American semiconductor manufacturers mainly use this package in circuits such as microprocessors and ASICs. The pin center distance is 0.635mm, and the pin number is about 84 to 196 (see QFP).

BQFP(quad flat package with bumper)

3. Butt welding PGA (butt joint pin grid array)

Another name for surface mount PGA (see surface mount PGA).

Butt welding PGA (butt joint pin grid array)

4. C-(ceramic)

Indicates the mark of the ceramic package. For example, CDIP stands for ceramic DIP. It is a mark that is often used in practice.

5. Cerdip

Ceramic dual in-line package sealed with glass, used for ECL RAM, DSP (digital signal processor) and other circuits. Cerdip with glass window is used for ultraviolet erasable EPROM and microcomputer circuit with EPROM inside. The pin center distance is 2.54mm, and the number of pins is from 8 to 42. In japon, this package is represented as DIP-G (G means glass seal).

6. Cerquad

One of the surface mount packages, the ceramic QFP under hermetic sealing, is used to package logic LSI circuits such as DSP. Cerquad with windows is used to encapsulate EPROM circuits. The heat dissipation is better than plastic QFP, and it can tolerate 1.5～2W power under natural air cooling conditions. But the packaging cost is 3 to 5 times higher than that of plastic QFP. The center distance of the pins has a variety of specifications such as 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and so on. The number of pins ranges from 32 to 368.

7. CLCC (ceramic leaded chip carrier)

Ceramic chip carrier with pins, one of the surface mount packages, the pins are led out from the four sides of the package in a T-shape. It is used to encapsulate the ultraviolet erasable EPROM and the microcomputer circuit with EPROM with windows. This package is also called QFJ, QFJ-G (see QFJ).

8. COB (chip on board)

Chip-on-board packaging is one of the bare chip mounting technologies. The semiconductor chip is hand-attached and mounted on the printed circuit board. The electrical connection between the chip and the substrate is realized by wire stitching, and the electrical connection between the chip and the substrate is realized by wire stitching. Resin covered to ensure reliability. Although COB is the simplest bare chip mounting technology, its packaging density is far inferior to TAB and flip-chip bonding technology.

9. DFP (dual flat package)

Double-sided lead flat package. It is another name for SOP (see SOP). There used to be this term, but it is basically not used now.

10. DIC (dual in-line ceramic package)

Another name for ceramic DIP (including glass seal) (see DIP).

11. DIL (dual in-line)

DIL is the abbreviation of dual in-line, dual in-line.

12. DIP (dual in-line package)

Dual in-line package. One of the plug-in packages, the pins are drawn from both sides of the package, and the package materials are plastic and ceramic.

DIP is the most popular plug-in package, and its application range includes standard logic ICs, memory LSIs, and microcomputer circuits.

The pin center distance is 2.54mm, and the number of pins is from 6 to 64. The package width is usually 15.2mm. Some packages with a width of 7.52mm and 10.16mm are called skinny DIP and slim DIP (narrow DIP) respectively. But in most cases, no distinction is made, and they are simply collectively referred to as DIP. In addition, ceramic DIP sealed with low-melting glass is also called cerdip (see cerdip).

13. DSO (dual small out-lint)

Two-sided lead small outline package. Another name for SOP (see SOP). Some semiconductor manufacturers use this name.

14. DICP (dual tape carrierpackage)

Two-sided lead-carrying package. One of TCP (Tape Carrier Package). The pins are made on the insulating tape and lead out from both sides of the package. Due to the use of TAB (automatic tape load welding) technology, the package outline is very thin. It is often used in liquid crystal display driver LSI, but most of them are customized products.

In addition, a 0.5mm thick memory LSI book package is in the development stage. In Japan, DICP is named DTP in accordance with EIAJ standards.

15. DIP (dual tape carrierpackage)

Same as above. The Japanese Electronic Machinery Industry Association standard names DTCP (see DTCP).

16, FP (flat package)

Flat package. One of surface mount packages. Another name for QFP or SOP (see QFP and SOP). Some semiconductor manufacturers use this name.

17, flip-chip

Flip-soldering the chip. One of the bare chip packaging technologies is to make metal bumps in the electrode area of the LSI chip, and then connect the metal bumps with the electrode area on the printed circuit board. The footprint of the package is basically the same as the chip size. It is the smallest and thinnest of all packaging technologies.

However, if the thermal expansion coefficient of the PCB substrate is different from that of the LSI chip, a reaction will occur at the joint, which will affect the reliability of the connection. Therefore, it is necessary to use resin to reinforce the LSI chip, and use a substrate material with substantially the same thermal expansion coefficient.

18. FQFP (fine pitch quad flatpackage)

Small pin center distance QFP. Usually refers to a QFP with a lead center distance of less than 0.65mm (see QFP).