PCB Tech - CPLD's PCB design power management architecture

As circuit board designs become more complex, they begin to push the performance of existing hardware/power management architectures to their limits. There are currently four most commonly used circuit board management architectures. Although all can be used to support these complex designs, they more or less need to make concessions or compromises in terms of design scalability, workload, or cost.

Recently, the fifth type of circuit board management architecture has appeared, which can provide the highest performance, safety and flexibility at present, while greatly reducing the design workload and construction cost. This article will discuss this new architecture, focusing on the power management functions it provides.

Overview

We usually divide a circuit board into two functional modules (Figure 1)-load management (Payload Management) and hardware management (Hardware Management). For most circuit boards, the load function accounts for 80% to 90% of the entire PCB area (data/control layer and/or processor). The remaining 10% to 20% is the hardware management part, which is used to perform hardware-level monitoring/control or housekeeping.

Until recently, a brand-new decentralized architecture has emerged, which is more scalable than other architectures and can be implemented at a lower BOM cost. In order to facilitate the understanding of the advantages of the distributed architecture, we first discuss how to build the power management function of the four most commonly used hardware management architectures (Figure 2-5), and then further explore the distributed architecture.

Comparison of power management architecture based on control PLD

CPLD-based power management and housekeeping, in this architecture, power management functions are added to the on-board control PLD (CPLD). The CPLD monitors the input power and the ‘Power Good’ signal of each DC-DC converter. Use CPLD to implement timing algorithm to generate ‘Enable’ signal for powering up the load circuit to avoid damage or logic errors. The CPLD can also generate logic signals, such as Reset and Power Good signals, to ensure that the load components can start operation when power is turned on or stop when power is turned off. It is also responsible for generating sequences to safely disable the power supply in the event of a power failure or detection of a fault. PLD is easy to support event-oriented solutions and can provide separate responses for different failure combinations.

CPLD-based hardware management system can realize power management and housekeeping functions

For this type of design, all power sequence, protection and control functions are implemented using CPLD, usually written in VHDL or Verilog.

advantage:

▪ low cost

▪ Intuitive architecture makes the timing logic of CPLD easy to adjust to new applications

▪ Use a design environment (commonly used Verilog) to realize the design

▪ The event-oriented architecture can respond differently to various failures in a flexible way

shortcoming:

▪ Because each power supply requires 2 signal channels, larger and more complex designs begin to face the challenge of more CPLD I/O ports and congestion of circuit boards

▪ Power Good detection is not accurate (usually 8% to 20% error rate) and the trend of unable to monitor the power supply voltage, resulting in reduced reliability

▪ Adding the automatic measurement function (monitoring the actual power supply voltage, not the Power Good signal), an A/D converter must be added, which increases the cost and complexity of the circuit board

▪ A board-level engineer (with digital circuit experience) is required to build the required functions. In many cases, this type of engineer is not an expert in power supply

Use power management IC to set power management, and use CPLD for housekeeping

In this functionally split architecture, a power management IC is responsible for monitoring and sequencing the DC-DC converter of the circuit board. Because the power management IC can directly monitor the voltage of the power supply, it can also perform fine-tuning and margining functions. The CPLD uses the Power Good state of the power supply to generate the necessary control, state, and housekeeping signals.

These designs often use GUI-based configuration tools to define power management IC functions, while CPLD logic is defined using VHDL or Verilog.

advantage:

▪ Reduce the number of CPLD I/O, because the ‘Enable’ function can be performed by the power management IC

▪ The board space is more generous, which can achieve a more simplified layout and fewer PCB layers

▪ By directly monitoring the power supply voltage, the power management IC can obtain more accurate overall system health information and improve system stability

shortcoming:

▪ Power management IC increases the BOM cost-especially when multiple components are required

▪ The architecture can provide event-oriented response, but if more than two power management ICs are deployed, it will increase the design complexity

▪ Adjusting sequences for more complex designs will become more difficult-especially when it comes to dividing functions for multiple power management ICs

▪ Because the design process must use multiple tools (GUI + VHDL/Verilog), it may require multiple engineers, and it will increase the design risk

Use CPLD to implement housekeeping, and PMBus to implement MCU-based power management functions. The architecture uses a microcontroller (MCU) to control the power sequence of the digitally controlled point of load (DPOL). The MCU uses the power management bus (PMBus) to manage DPOL-PMBus is a two-wire communication protocol based on the I2C bus. The CPLD is responsible for on-board housekeeping functions and controlling any point-of-load DC-DC converter with an analog control interface (APOL). In order to simplify the software design, most MCU-based power management designs adopt time-series schemes.

There is another potential disadvantage of software-based power management, which is the need for longer fault response time (usually 10 to 15 milliseconds, while the response time of CPLD is microseconds). For certain faults that require faster response time (or event-oriented sequence), CPLD can be added as a second protection measure.

Realization of software-based power management requires VHDL or Verilog for MCU software and CPLD design.

advantage:

▪ The design is very easy to adjust (only for time-based series)

▪ Abundant software development tools make MCU-based solutions faster and more convenient for debugging.

▪ Upgrade the firmware to quickly change the design

▪ Simplify PCB design-the wiring around DPOL is more surplus

shortcoming:

▪ More expensive BOM cost

▪ It is difficult to adjust the design for event-oriented sequence requirements

▪ requires multiple design tools (Verilog/VHDL+ software)

Summarize

With the increasing design complexity of PCB-level systems, hardware management systems account for an increasing proportion of both design workload and BOM cost. The use of CPLD and POL power supplies to implement some or all of the management functions can alleviate the difficulties caused by the above-mentioned trends, but at this time the cost has become a stumbling block. Now, a distributed hardware management architecture is available, and CPLDs can be connected to low-cost sensing components through a 3-wire serial link. In addition to reducing design complexity, PCB space requirements, and BOM cost, the architecture can also be built using a variety of analog and digital engineers' tools.