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High Dynamic Performance ADC and RF Devices in Digital RF Receivers
2021-07-30
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Author:Evian

Base station system (BTS) needs to meet the index requirements of signal link while meeting various standards. This paper introduces some signal link devices that dynamic high performance ADC and RF devices in digital RF receivers, such as high dynamic performance ADC, variable gain amplifier, mixer and local oscillator, and introduces their use in typical base stations in detail, which can meet the requirements of base station system for high dynamic performance, high intercept performance and low noise.


Most digital receivers have high requirements for high-performance analog-to-digital converter (ADC) and simulator. For example, the cellular base station digital receiver requires sufficient dynamic range to process large interference signals, so as to demodulate the useful signals with low level. Maxim's 15 bit 65msps analog-to-digital converter max1418 or 12 bit 65msps analog-to-digital converter max1211, coupled with 2GHz max9993 or 900MHz max9982 integrated mixer, can provide excellent dynamic characteristics for the two-stage key circuits of the receiver. In addition, Maxim's intermediate frequency (if) digital adjustable gain amplifiers (DVGA) max2027 and max2055 can provide high third-order output cut-off point (OIP3) in many systems, And meet the gain adjustment range required by the system.

Max1418 ADC chip and circuit

Max1418 ADC chip and circuit

Max1418 ADC chip and circuit



Cellular base station (BTS: base station transceiver) is composed of several different hardware modules, one of which is the transceiver (TRX) module that performs RF receive (Rx) and transmit (TX) functions. In the old analog amps and TACs BTS, one transceiver can only be used to process one full duplex RX and TX RF carrier. In order to achieve the required call coverage, many transceivers are required to provide enough carriers. Today, worldwide, analog technology has been replaced by CDMA and WCDMA, and GSM was adopted in Europe 10 years ago. In CDMA, multiple calling users use the same RF frequency, so that one transceiver can process the signals of multiple calling users at the same time. Up to now, there have been a variety of CDMA and GSM design schemes. BTS manufacturers have also been committed to exploring methods to reduce cost and power consumption. Optimizing single carrier solutions or developing multi carrier receivers are effective solutions. Fig. 1 is a structural block diagram of an undersampling receiver commonly used in BTS equipment.

Figure 1. Structure block diagram of undersampling receiver

Figure 1. Structure block diagram of undersampling receiver



In Figure 1, Maxim's 2GHz max9993 and 900MHz max9982 mixers can provide the required gain and linearity for many designs, and have very low coupling noise, so that those passive mixers with high loss are no longer needed. Max2027 and max2055 work in the first and second medium frequency stages of the receiver. OIP3 of these two devices can reach + 40dbm in the whole gain adjustment range. In the circuit shown in Figure 1, max1418 (15 bit, 65msps) and max1211 (12 bit, 65msps) are used as data converters. In addition, Maxim's data converter products also have other devices with sampling rate, which can meet most design requirements. If the second down converter in Fig. 1 is omitted (shown in the dotted line), the circuit shown in Fig. 1 becomes a single down converter structure. Maxim's low noise ADC: max1418.

The structure of the undersampling receiver shown in Fig. 1 has strict requirements for the noise and distortion of the ADC. In the receiver, the useful signal with low level is digitized alone or accompanied by useless and large amplitude signals that need to be paid more attention. Therefore, in order to make the receiver work normally, the effective noise coefficient of ADC should be calculated according to the extreme conditions of these two signals (i.e. the minimum useful signal and the maximum useless signal). For small analog input signals, thermal noise and quantization noise dominate the noise base of ADC, which determines the noise figure (NF) of ADC.

In fact, the effective noise coefficient of ADC under small signal condition is determined, and the cascade noise coefficient of analog circuit (RF or if) is determined accordingly. The minimum power gain of ADC front stage circuit shall meet the noise coefficient requirements of receiving circuit. Generally, the power gain value is the upper limit of the maximum blocking level or maximum interference level allowed by the receiver before the ADC overload. In BTS, if AGC is not used, the dynamic range of ADC can not meet the requirements of circuit noise coefficient (receiver sensitivity) and maximum blocking. AGC circuit can be placed in RF or if level circuit or AGC circuit in two-stage circuit.

Other products of max1418 series are particularly suitable for baseband applications with feinput = fclock/2. When the converter works in this frequency range, the best dynamic range will be obtained by using these devices with excellent baseband characteristics. These products include max1419 for 65msps clock rate and max1427 for 80msps clock rate. Their baseband SFDR (no stray dynamic range) can reach 94.5dbc.

Table 1 lists the main technical parameters of max1418

Table 1 lists the main technical parameters of max1418


When the LSB is not connected, the max1418 can also work with 14 bit interface devices. In this way, SNR will be slightly lost, while SFDR will not be affected.

Figure 2 shows the noise distribution of ADC without blocking. Here, it is assumed that the total cascade noise coefficient of all analog circuits before ADC is 3.5db, and the design goal is that the deterioration of the total noise coefficient caused by ADC does not exceed 0.2db, so as to meet the sensitivity requirements of CDMA base station receiver. Such a noise coefficient value should leave enough margin for the air interface, but the final result depends on the requirements of EB / no (ratio of bit energy to noise power spectral density) of the last stage detector. Based on the thermal noise + quantization noise substrate of max1418 in Table 1, when the device clock is 61.44msps (50x chip rate), its equivalent noise coefficient is 26.9db. Due to the process gain control, the ADC noise in 1.23mhz CDMA channel bandwidth is 14dB lower than that in Nyquist broadband. In general, in order to obtain the cascade noise figure of 3.7dB receiver, the total gain should reach 36dB.

Figure 2. ADC noise distribution without blocking

Figure 2. ADC noise distribution without blocking


When the front-end gain of ADC is 36dB, the single tone blocking level exceeding - 30dBm at the antenna end will exceed the input range of ADC. cdma2000 ® The cellular base station standard stipulates that the maximum blocking level allowed at the antenna end is - 30dBm. At this time, the front-end gain needs to be reduced by 6dB, so that the maximum blocking signal allowed to be added to the ADC is larger within the margin range allowed by the standard specification. Assuming a margin of 2dB is left, the maximum blocking level at the antenna end will become - 26dbm and the maximum allowable input signal of ADC will become + 4dbm when the front-end gain is reduced by 6dB (see Fig. 3). When single tone blocking occurs, the cellular standard allows the total interference (noise + distortion) to deteriorate by 3dB relative to the reference sensitivity, but how to distribute the 3dB between noise and distortion is left to the designer.

Assumption: in case of blocking signal, AGC gain is 6dB, and the design allows RF front-end cascade noise plus distortion to reduce NF by 1dB (nominal value is 3.5db). When the front-end gain of ADC is only 30dB, the SNR of ADC determines that its effective noise figure is 29.4db, and the noise figure of cascade receiver under 'blocking condition' is 5.7db, which is 2dB lower than the 3.7dB noise figure calculated according to receiver sensitivity. Since the spurious characteristics are not taken into account in this calculation, the spurious free dynamic range (SFDR) of ADC allows an additional reduction of 1dB. When there is a blocking signal, SINAD can be used to calculate the effective NF, and the noise and SFDR base values are no longer calculated respectively.

Figure 3. ADC noise response in case of blocking

Figure 3. ADC noise response in case of blocking


Max11211 allows a down conversion structure

If enough SNR and SFDR indexes can be obtained in the higher if segment, the under sampling circuit can be used in the primary down conversion structure. Max11211 12 bit and 65msps converter are designed with this structure. Its pins are compatible with the upcoming 80msps and 95msps converters. This series of devices can directly sample the input signal if number with frequency up to 400MHz. In addition, it also has other advanced performance, such as clock input can be differential signal or single terminal signal, The duty cycle of clock can be between 20% and 80%, in addition, it also has data effective indicator (to simplify clock and data sequence), and it adopts small-sized 40 pin QFN (6mm x 6mm x 0.8mm) package, binary complement code and gray code digital output format. Table 2 lists the typical AC characteristics of max11211 with an analog input frequency of 175mhz.

Chart2. MAX1211 Electrical characteristics

Chart2. MAX1211 Electrical characteristics



Compared with the structure of the secondary frequency conversion, the primary converter has obvious advantages. The number of components and the space of the circuit board can be reduced by about 10% and the cost can be saved by $10 to $20 due to the elimination of the second down conversion mixer, the second intermediate frequency gain circuit and the second LO synthesizer.

Consideration of the stray of different structures. If the number of components, board space and power consumption and cost need to be further saved, the primary frequency conversion structure given below can be adopted. It is assumed that the designed CDMA2000 receiver works in the PCs band, with a sampling rate of 61.44msps, a synthesizer reference frequency of 30.72mhz, and the center of the first intermediate frequency selected at the 6th Nyquist band of 169MHz and a bandwidth of about 1.24mhz. For DDS structure, the same 169MHz first intermediate frequency and the second intermediate frequency center frequency are 46.08mhz of the second order Nyquist band.


Hypothetical spurious characteristics for SDC and DDC architectures

Hypothetical spurious characteristics for SDC and DDC architectures



Table 3 lists the assumed conditions for RF carrier stray search near the upper end of PCs band when single carrier, primary down conversion (SDC) and two down frequency (DDC) structures are used. For SDC structure, 134 harmonic components can be found in RF receiving frequency, receiving mirror frequency band, if band and if mirror frequency band. Most of these spurious signals have higher order and will not reduce the performance of reception. For DDC structure, stray search will find more than 2400 harmonics, which is more than 18 times that found under SDC structure. These harmonics are distributed in RF receiving frequency band, receiving mirror frequency band, first level if frequency band, first level if mirror frequency band, second level if frequency band and second level if mirror frequency band. For the stray signals from the high order clock harmonic and synthesizer reference frequency, it can be suppressed by carefully considering the layout of the circuit board or adding filtering in the design. However, it is difficult to suppress a large number of the stray components with lower order.


Maxim's IF amplifier: max2027 & max2055

Maxim also provides a digital control gain of 1dB per stage and high performance if amplifier. Max2027 is a digital control gain amplifier (DVGA). It uses single input / single output mode, which can work in the frequency range of 50MHz to 400MHz, and its maximum gain noise coefficient is only 5dB. Max2055 is a DVGA with single input / differential output, which can drive high performance ADC in the frequency range of 30MHz to 300MHz. A step-up transformer can be used between the differential output of max2055 and ADC differential input. The transformer provides differential drive, which is conducive to the balance between output signals. The two DVGA work at 5V bias and have OIP3 of +40dbm throughout the gain setting range. For more details, please refer to the relevant information on the maxim website (china.maximantegraded.com). Maxim's high linear mixer: max9993 & max9982.

In the receiving circuit, mixer often bears the larger input signal which has more strict performance requirements. In ideal state, the amplitude and phase of the mixer output signal are proportional to the amplitude and phase of the input signal, and the proportional relationship is not related to LO signal. According to this assumption, the amplitude response of mixer is linear with RF input, and is independent of Lo input signal.

However, the nonlinearity of mixer will produce some unwanted mixing signals, called spurious response, which are the response of IF band generated by signals arriving at RF port of mixer and not expected to appear. The useless stray signal will interfere with the work of useful RF signal. If frequency of mixer can be given by the following formula:

 If = ± MFRF ± nflo, if, RF and lo are signal frequencies of their respective ports, and m and N are the harmonic orders after mixing RF and LO signals.


The integrated (or active) balanced mixers (such as max9993 and max9982) are concerned because of their performance better than passive mixing schemes. When m or n is even, balanced mixer can suppress some stray response, and the second harmonic performance is better. The ideal double balanced mixer can suppress all responses with an even number of M or n (or both). In the double balanced mixer, if, RF and lo ports are isolated from each other. The mixer can overlap in if, RF and LO frequency bands by using a reasonably designed unbalanced transformer. Max9993 and max9982 features include: low noise coefficient, LO buffer, low Lo drive, Lo switch that allows two Lo inputs, excellent Lo noise characteristics, etc. in addition, RF unbalanced transformer is also integrated in RF and lo ports.

 These mixers of Maxim are embedded with lo buffers with excellent Lo noise performance, which reduces the requirements for lo power supply. Generally, the combination of Lo noise and input blocking signal with high level will reduce the reception sensitivity. Max9993 and max9982 contain low noise Lo buffers, which can reduce the influence on the reception sensitivity in case of blocking. For example, suppose that the edge band noise of VCO input signal is -145dbc/hz, and the typical Lo noise characteristic of max9993 is -164dbc/hz, so that the compound sideband noise only drops 0.05dbc/hz to -144.95dbc/hz. In this way, the user not only provides a low level LO signal for the mixer, but also ensures that the mixing characteristics of the receiver will not be reduced by the performance of the built-in LO buffer in max9993.

In addition, there is also a kind of tricky second-order spurious response, also known as half if (1/2 if) spurious response. For low-end injection, the order of mixer is: M = 2, n = -2; For high end injection, the mixer order is: M = -2, n = 2. The input frequency that causes the half if parasitic response is lower than the desired RF frequency when the low injection is low (Fig. 4). The desired RF frequency is 1909mhz and 1740mhz LO frequency, and the IF frequency is 169MHz. Although the RF and if carrier bandwidth of CDMA is 1.24mhz, it is represented here as a single frequency signal with a central carrier frequency. In this example, useless signals at 1824.5mhz cause a half if stray component of 169MHz:


From this, we can get: 

2 x 1824.5MHz - 2 x 1740MHz = 169MHz

Figure 4. Location of useful FRF, Flo, FIF and useless fhalf if frequencies

Figure 4. Location of useful FRF, Flo, FIF and useless fhalf if frequencies


The total suppression (also known as 2x2 spurious response) can be predicted according to the second cut-off point IP2 of the mixer. Figure 5 shows the 2x2 IMR or spurious value (max9993 data from Maxim). Note: the signal level in the figure is the mixer input level calculated by input IP2 (IIP2) performance. The specific calculation formula is as follows:


Since the typical stray response 2rf - 2lo provided by Maxim max9982 900MHz active filter is 65dbc, the calculation method of its IIP2 is as follows:

Figure 5. Calculate the second cut-off point of the mixer input signal, IIP2

Figure 5. Calculate the second cut-off point of the mixer input signal, IIP2



When the receiver gain requirement is not high, Maxim's 15 bit ADC max1418 has excellent noise performance, so it can withstand large blocking level or interference level with the smallest AGC. Max1211 ADC series products are suitable for primary frequency conversion receiving structure, and its first if input frequency can reach 400MHz. In addition, Maxim's max9993 and max9982 mixers can provide the required linearity, low noise figure and high power gain, so the passive filter can be omitted in the receiver design process. The typical value of OIP3 of max2027 and max2055 DVGA in the whole gain adjustable range is about + 40dbm. The receiver composed of these elements can improve the performance of low-cost solutions to a higher level. This paper introduces some signal link devices that high dynamic performance ADC and RF devices in digital RF receivers, if you have any questions welcome to communicate with iPcb.