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PCB Tech
Introduction to the problem of bus contention in PCB repair
PCB Tech
Introduction to the problem of bus contention in PCB repair

Introduction to the problem of bus contention in PCB repair

2021-11-06
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Author:Downs

When performing an online function test on a PCB bus device (such as 74245), the test fails because its bidirectional input/output pins may be affected by other devices connected to it via the bus. The bus device may be in the enabled state after the board under test is powered on, so that its output/input pins are not in the tri-state high impedance state. Test the result window when bus contention occurs in the test bus device. In order to eliminate the influence of bus contention and pass the test of the tested chip, the user must isolate the related bus devices.

A test result showed that the 3rd, 4th, and 9th pins of 74245 did not flip, and the test failed. At this time, the user should check the dynamic impedance of each pin of the chip from the pin status to determine whether there is a pin that is short-circuited to the ground or has a very low resistance to ground (less than 5 ohms). From the upper right picture, you can notice that the impedance of the 11th, 16th and 17th pins to ground is about 290 ohms, and the impedance of the other output and input pins to ground are between 17-23 ohms. The former indicates that the pin is in a logic high state, and the latter indicates that the pin is in a logic low state. The second pin passed the test and was not affected by bus contention because its output pin can withstand the pull-down effect of the connected device.

The user must be able to distinguish whether the test failure is caused by bus contention or caused by damaged device functions. In this example, the reason for the test failure is bus contention. In order to perform a complete test on the device, the user must isolate the relevant bus device and make its output pin in a high-impedance state without affecting the device under test.

When the third pin of the chip is used as an output pin, it is pulled down by the connected chip and cannot be flipped. When pin 3 is used as an input pin, since the maximum drive current of QT200 is 650 mA, even if pin 3 is pulled down by other chips, QT200 can still pull pin 3 to a high potential, so pin 17 can be tested. If the function of the chip is damaged, it is impossible to pass the output test on pin 17 at this time.

pcb board

The actual test result is that the 17th pin output test passed, obviously not the function of the chip is damaged, but the bus contention problem.

How to determine which chip causes PCB bus contention and must be isolated?

If the user has the circuit schematic diagram of the tested board, first find out all other bus chips connected to the tested chip. Usually, the bus chips in the circuit can be divided into the following three categories:

a, the enable terminal is connected to the output terminal of other chips;

b. The enable terminals of two or more bus chips are connected;

c. The enable terminal is directly connected to the ground or +5v power supply.

For the first type of bus chip, isolation should be set for each enable terminal by setting the corresponding logic level on the flying lead channel of QT200 (from FC0 to FC7), and then connect to these enable terminals respectively; for the second type For bus chips, only one isolation channel is provided, which is connected to the enable terminal of one of the chips; for the third type of bus chip, isolation settings cannot be directly performed because the isolation channel cannot implement reverse drive on its enable terminal. The general processing principle is to set the first two types of bus chips first to see whether the test results of the tested chip are satisfactory (that is, the quality of the chip can be judged from the results), if it is, the isolation of the third type of bus chip is not considered; if Still dissatisfied, and then take measures to isolate the third type of bus chip. Generally, the secant method is used to disconnect the enable terminal from the ground or +5v power supply, and then isolate it.

Retest the chip after setting the isolation point. If the test passes, then remove the set isolation channels one by one and retest. When the test fails, the bus chip whose isolation setting is removed is the chip that generates bus contention. Reconnect the isolation channel of the chip, and continue to check other undetermined bus chips according to the above method. Until the last find out all the bus chips that need to be isolated (in the board learning mode, start the notepad, record which chips need to be isolated for the test of which bus chips, which will be of great help when repairing the broken board).

If the user does not have a circuit diagram, he can use the scan test in the QSM/VI test method to find out other bus chips connected to the chip under test. The specific method is: directly enter the interactive QSM/VI test window from the ICFT test mode, customize a name of the chip to be tested, set the number of pins to 40, the measurement frequency to 312Hz, and use the QT200 cable for circuit tracking (there are two A 20-pin fixture), connect fixture 1 to the bus chip under functional test (the first pin of the fixture faces the first pin of the chip), and connect fixture 2 to any other bus chip on the board under test, and then Start the scan test. If there is a connection between the two chips, it will be displayed in a window on the screen. Among them, pins 1-20 represent the chip connected to fixture 1, and pins 21-40 represent the chip connected to fixture 2. If the 5th pin and the 35th pin in the window are marked with the L1 symbol, it means that the 5th pin of the first chip is connected to the 15th pin of the second chip.

How to use the digital oscilloscope function of the system to judge the quality of the bus devices?

When testing bus devices, if the quality of the device cannot be judged by isolation, you can use the latest function of this system—digital oscilloscope (DSO) to test. The basic operation method is as follows:

Resolder the crystals soldered on the PCB under test so that the board has a normal clock running.

Connect the test probe to the appropriate channel (note: the selected probe channel is different for different versions of the system software)

Press the DSO key from the toolbar in the test window to start the digital oscilloscope mode.

Turn on the power supply of the tested PCB board

Connect the probes to different pins of the tested bus device in turn, and you can see the actual signal of the tested pin on the screen. If the signal changes from high to low, it means that the pin functions normally. If the signal potential is fixed between 2v and 1.8v, special attention should be paid to the pin. This may be because the function of the pin is damaged, or the pin is an output pin in an open circuit state. At this time, the 7404 chip near the crystal can be detected, because this chip is often used in clock circuits. Test the output pin of 7404 with a probe, there should be a waveform signal  . If not, check whether the power supply of the tested PCB board is normal and whether the crystal is damaged. Note that the oscilloscope should select 100K impedance when detecting the clock signal, so as to avoid the influence on the crystal oscillator circuit.

In order to detect whether the pin is in the floating state, the impedance of the oscilloscope can be selected as 10K. If the pin is indeed floating (its impedance is greater than 1 megaohm), then when the probe touches the pin, the 10K impedance will pull the pin to a low level. If the pin is not left floating, but has a fixed level, the probe will not pull it low. From this, the true state of the PCB pins can be judged.