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PCB Tech
What are the methods for PCB printed circuit board vias
PCB Tech
What are the methods for PCB printed circuit board vias

What are the methods for PCB printed circuit board vias

2021-11-07
View:33
Author:Downs

one. The basic concept of vias

Via is one of the important components of multi-layer PCB printed circuit boards, and the cost of drilling usually accounts for 30% to 40% of the cost of PCB manufacturing. Simply put, every hole on the PCB printed circuit board can be called a via. From the point of view of function, vias can be divided into two categories: one is used for electrical connections between layers; the other is used for fixing or positioning devices. From the perspective of the PCB process, these vias are generally divided into three categories, namely blind vias, buried vias and through vias. Blind vias are located on the top and bottom surfaces of the printed circuit board and have a certain depth. They are used to connect the surface line and the underlying inner line. The depth of the hole usually does not exceed a certain ratio (aperture). Buried hole refers to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board. The above-mentioned two types of holes are located in the inner layer of the circuit board, and are completed by a through-hole forming process before lamination, and several inner layers may be overlapped during the formation of the via. The third type is called a through hole, which penetrates the entire circuit board and can be used for internal interconnection or as a component mounting positioning hole. Because the through hole is easier to implement in the process and the cost is lower, most of the printed circuit boards use it instead of the other two types of through holes. The following via holes, unless otherwise specified, are considered as via holes.

Via hole of printed circuit board

From a design point of view, a via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill. The size of these two parts determines the size of the via. . Obviously, in high-speed, high-density PCB design, designers always hope that the smaller the via hole is, the better, so that more wiring space can be left on the board. In addition, the smaller the via hole, the parasitic capacitance of its own. The smaller it is, the more suitable it is for high-speed circuits. However, the reduction in hole size also brings about an increase in cost, and the size of vias cannot be reduced indefinitely. It is limited by process technologies such as drilling and plating: the smaller the hole, the more drilling The more difficult the hole processing process, the longer it takes, and the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, it is impossible to ensure that the hole wall can be uniformly plated with copper. For example, the thickness of a normal 6-layer PCB board (through hole depth) is about 50Mil, so the minimum drilling diameter that a general PCB manufacturer can provide can only reach 8Mil.

two. Parasitic capacitance of via

pcb board

The via itself has a parasitic capacitance to the ground. If it is known that the diameter of the isolation hole on the ground layer of the via is D2, the diameter of the via pad is D1, the thickness of the PCB printed circuit board is T, and the board substrate dielectric is The constant is ε, then the parasitic capacitance of the via is approximately as follows:

C=1.41εTD1/(D2-D1)

The main effect of the parasitic capacitance of the via on the circuit is to extend the rise time of the signal and reduce the speed of the circuit. For example, for a PCB with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, then we can approximate the via using the above formula The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF, the rise time change caused by this part of the capacitance is: T10-90=2.2C(Z0/2)=2.2 x0.517x(55/2)=31.28ps. It can be seen from these values that although the effect of the rise delay caused by the parasitic capacitance of a single via is not obvious, if the via is used multiple times in the trace to switch between layers, the designer should still consider carefully.

three. Parasitic inductance of vias

Similarly, there are parasitic inductances along with the parasitic capacitance of the vias. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of the vias is often greater than the impact of the parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can simply calculate the parasitic inductance of a via with the following formula:

L=5.08h[ln(4h/d)+1]

Where L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center hole. It can be seen from the formula that the diameter of the via has a small influence on the inductance, and the length of the via has the greatest influence on the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is: XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when high-frequency currents pass. Special attention should be paid to the fact that the bypass capacitor needs to pass through two vias when connecting the power plane and the ground plane, so that the parasitic inductance of the vias will increase exponentially.