PCB Tech - Improve circuit design rules to improve testability

With the continuous improvement of miniaturization, components and wiring technology have also made great developments, such as highly integrated micro ICs packaged in BGA shells, and the reduction of insulation spacing between conductors to 0.5mm. These are just two examples. The wiring design of electronic components has an increasing influence on whether the test in the future production process can be carried out well. Here are some important rules and practical tips.

By complying with certain regulations (DFT-Design for Testability), the preparation and implementation costs of production tests can be greatly reduced. These regulations have been developed over the years. Of course, if new production technologies and component technologies are adopted, they must be expanded and adapted accordingly. As the size of electronic products becomes smaller and smaller, two particularly noticeable problems have emerged: one is that there are fewer and fewer circuit nodes that can be contacted; the other is methods like in-circuit-test. Application is restricted. In order to solve these problems, corresponding measures can be taken on the circuit layout, new test methods and innovative adapter solutions can be adopted. The solution to the second problem also involves making the test system that was originally used as an independent process undertake additional tasks. These tasks include programming memory components through test systems or implementing integrated component self-tests (Built-in Self Test, BIST, built-in self-test). Transferring these steps to the test system, overall, it still creates more added value. In order to implement these measures smoothly, there must be corresponding considerations in the product research and development stage.

1. What is testability

The meaning of testability can be understood as: test engineers can use the simplest possible method to detect the characteristics of a certain component to see if it can meet the expected function. Simply put:

How simple is the method for testing whether the product meets the technical specifications?

How fast can I write a test program?

To what extent has the product failure been found to be comprehensive?

How simple is the method of accessing the test point?

In order to achieve good testability, mechanical and electrical design regulations must be considered. Of course, to achieve the best testability, you need to pay a certain price, but for the entire process, it has a series of benefits, so it is an important prerequisite for the successful production of the product.

2. Why develop test-friendly technology

In the past, if a product could not be tested at the previous test point, then the problem was simply moved to a test point. If the product defect cannot be found in the production test, the identification and diagnosis of the defect will simply be transferred to the function and system test.

On the contrary, today people try to find defects as early as possible. Its benefits are not only low cost, but more importantly, today's products are very complex, and some manufacturing defects may not be detected at all in functional tests. For example, some components that need to be pre-installed with software or programming have such a problem. (Such as flash memory or ISPs: In-System Programmable Devices). The programming of these components must be planned in the development stage, and the test system must also master this programming.

It costs some money to test friendly circuit designs, however, it costs more to test difficult circuit designs. Testing itself has a cost, and the cost of testing increases as the number of test levels increases; from online testing to functional testing and system testing, testing costs are getting higher and higher. If you skip one of the tests, the cost will be even greater. The general rule is that the coefficient of increase for each additional level of test cost is 10 times. Through the test-friendly circuit design, faults can be found early, so that the money spent on the test-friendly circuit design can be quickly compensated.

3. How do documents affect testability

Only by making full use of the complete data in the component development, it is possible to compile a test program that can fully discover the failure. In many cases, close cooperation between the development department and the testing department is necessary. The documentation has an indisputable impact on the test engineer’s understanding of component functions and the formulation of test strategies.

In order to circumvent the problems caused by lack of documentation and poor understanding of component functions, test system manufacturers can rely on software tools that automatically generate test patterns according to the random principle, or rely on non-vector comparisons. Non-vector methods can only be counted as one. Kind of expedient solution.

The complete documentation before the test includes parts list, circuit design data (mainly CAD data) and detailed information about the functions of the service components (such as data sheets). Only when all the information is mastered can it be possible to compile test vectors, define component failure patterns or make certain pre-adjustments.

Certain mechanical data are also important, such as those needed to check whether the components are well welded and whether they are positioned. Finally, for programmable components, such as flash memory, PLD, FPGA, etc., if they are not programmed at the last installation, they must be programmed on the test system, and the respective programming data must also be known. The programming data of the flash device should be intact. If the flash chip contains 16Mbit data, it should be able to use 16Mbit, which can prevent misunderstanding and avoid address conflicts. For example, if a 4Mbit memory is used to provide only 300Kbit data to a component, this situation may occur. Of course, the data should be prepared into a popular standard format, such as Intel’s Hex or Motorola’s S record structure. Most test systems, as long as they can program flash or ISP components, can interpret these formats. Many of the information mentioned above, many of which are also necessary for component manufacturing. Of course, there should be a clear distinction between manufacturability and testability, because this is a completely different concept, which constitutes a different premise.

4. Mechanical contact conditions with good testability

If the basic rules of mechanics are not considered, even circuits with very good testability in electrical aspects may be difficult to test. Many factors can limit electrical testability. If the test points are not enough or too small, it will be difficult for the probe bed adapter to reach every node of the circuit. If the position error and size error of the test point are too large, the problem of poor test repeatability will occur. When using the probe bed adapter, you should pay attention to a series of recommendations regarding the size and positioning of the clamping hole and the test point.

5. Electrical prerequisites for best testability

Electrical preconditions are as important to good testability as mechanical contact conditions, and both are indispensable. A gate circuit cannot be tested. The reason may be that the start input terminal cannot be contacted through the test point, or the start input terminal is in the package and cannot be accessed from the outside. In principle, the two conditions are both bad. Make the test impossible. When designing the circuit, it should be noted that all components to be tested by the online test method should have a certain mechanism so that each component can be electrically insulated. This mechanism can be realized by prohibiting the input terminal, which can control the output terminal of the component in a static high-ohmic state.

Although almost all test systems can bring the state of a node to any state in a backdriving manner, it is better to prepare a prohibited input for the involved node. First, bring the node to a high-ohm state. Then add the corresponding level "gently".

Similarly, the beat generator is always disconnected directly from the back of the oscillator through the start lead, gate circuit or plug-in bridge. The start input terminal must not be directly connected to the circuit, but connected to the circuit through a 100 ohm resistor. Each component should have its own start, reset or control pin. It must be avoided that the start input terminals of many components share a resistor and are connected to the circuit. This rule also applies to ASIC components, these components should also have a pin, through which the output can be brought to a high-ohm state. If the component can be reset when the operating voltage is turned on, it is also very helpful for the tester to initiate a reset. In this case, the component can simply be placed in a prescribed state before testing.

The lead pins of unused components should also be accessible, because short circuits not found in these places may also cause component failure. In addition, unused gate circuits are often used for design improvement in the future, and they may be changed to the circuit. So it is also important that they should be tested from the beginning to ensure the reliability of their workpieces.

6. Improve testability

Suggestions for improving testability when using probe bed adapters

Hold-down hole

Diagonal configuration

Positioning accuracy is ±0.05mm (±2mil)

The diameter accuracy is ±0.076/-0mm (+3/-0mil)

The positioning accuracy relative to the test point is ±0.05mm (±2mil)

The distance from the edge of the component is at least 3mm

No penetrating contact

Test point

As square as possible

The diameter of the test point is at least 0.88mm (35mil)

The measurement point size accuracy is ±0.076mm (±3mil)

The accuracy of the interval between test points is ±0.076mm (±3mil)

The test point interval should be 2.5mm as much as possible

Tinned, the end face can be directly welded

At least 3mm from the edge of the component

All test points should possibly be on the back of the plug-in board

The test points should be evenly distributed on the plug-in board

Each node has at least one test point (100% channel)

Spare or unused gate circuits have test points

The multiple external test points of the power supply are distributed in different positions

Component logo

Logo text in the same direction

Model, version, serial number and bar code are clearly identified

The name of the component should be clearly visible, and should be marked as directly next to the component as possible

7. About flash memory and other programmable components

The programming time of flash memory is sometimes very long (up to 1 minute for large memories or memory banks). Therefore, reverse drive of other components is not allowed at this time, otherwise the flash memory may be damaged. In order to avoid this situation, all components connected to the control line of the address bus must be placed in a high-ohm state. Similarly, the data bus must be able to be placed in an isolated state to ensure that the flash memory is empty and can be programmed for the next step.

In-system programmable components (ISP) have some requirements, such as products from companies such as Altera, XilinX, and Latuce, as well as other special requirements. In addition to the mechanical and electrical preconditions for testability, the possibility of programming and validating data should also be guaranteed. For Altera and Xilinx components, a serial vector format (Serial Vector Format SVF) is used, which has almost developed into an industry standard recently. Many test systems can program such components and use the input data in the serial vector format (SVF) to test the signal generator. These components are programmed through the boundary scan key (Boundary-Scan-Kette JTAG), and a series of data formats are also programmed. When collecting programming data, it is important to consider all the component chains in the circuit, and not to restore the data only to the components to be programmed.

When programming, the automatic test signal generator takes the entire component chain into consideration and connects other components to the bypass model. On the contrary, Lattice requires data in JEDEC format and is programmed in parallel through the usual input and output terminals. After programming, the data is also used to check component functions. The data provided by the development department should be as easy as possible for the test system to be directly applied, or it can be applied through simple conversion.

8. What should be paid attention to for boundary scan (JTAG)

The components based on the fine grid of complex components provide test engineers with only a few accessible test points. It is still possible to improve testability at this time. For this, boundary scan and integrated self-test technology can be used to shorten the test completion time and improve the test effect.

For development engineers and test engineers, a test strategy based on boundary scan and integrated self-test technology will definitely increase costs. Development engineers must use boundary scan components (IEEE-1149.1-standard) in the circuit, and try to make the corresponding specific test pins accessible (such as test data input-TDI, test data output-TDO, test clock frequency) -TCK and test mode selection -TMS and ggf. Test reset). The test engineer develops a boundary scan model (BSDL-Boundary Scan Description Language) for the component. At this time, he must know what boundary scan functions and instructions the relevant components support. The boundary scan test can diagnose short circuits and open circuits down to the lead level. In addition, if the development engineer has specified, the automatic test of the component can be triggered by the boundary scan command "RunBIST". Especially when there are many ASICs and other complex components in the circuit, there is no usual test model for these components. Through boundary scan components, the cost of developing test models can be greatly reduced.

The degree of time and cost reduction is different for each component. For a circuit with IC, if 100% discovery is required, about 400,000 test vectors are needed. By using boundary scan, the number of test vectors can be reduced to hundreds under the same fault discovery rate. Therefore, the boundary scan method has special advantages under the condition that there is no test model or the nodes of the contact circuit are restricted. Whether to use boundary scan depends on the increased cost of development, utilization and manufacturing. Boundary scan must meet the requirements of the time to find faults, test time, time to enter the market, and the cost of the adapter.