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Signal Integrity-From the PCB layout of the WiFi transceiver to see the design method of the power supply and grounding of the RF circuit
2021-08-20
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Author:IPCB

The circuit PCB Board layout of radio frequency (RF) circuits should be carried out on the basis of understanding the basic principles of circuit board structure, power supply wiring and grounding. This article discusses the relevant basic principles, and provides some practical, proven power wiring, power bypass and grounding techniques, which can effectively improve the performance indicators of RF design. Considering that the PLL spurious signal in the actual design is very sensitive to the power coupling, grounding and the position of the filter element, this article focuses on the method of suppressing the PLL spurious signal. To illustrate the problem, this article uses the PCB layout of the MAX2827 802.11a/g transceiver as a reference design.

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Figure 1: Vcc wiring in star topology


When designing an RF circuit, the design of the power supply circuit and the layout of the circuit board are often left after the design of the high-frequency signal path is completed. For designs that have not been carefully considered, the power supply voltage around the circuit is prone to erroneous output and noise, which will further affect the performance of the RF circuit. Reasonable distribution of PCB layers, the use of star topology Vcc leads, and the addition of appropriate decoupling capacitors to the Vcc pin will help improve the performance of the system and obtain the best indicators.


Basic principles of power wiring and bypass


The wise PCB layer assignment is convenient to simplify the subsequent wiring processing. For a four-layer PCB (a commonly used circuit board in WLAN), in most applications, the top layer of the circuit board is used to place components and RF leads, and the second layer is used as the system Ground, the power part is placed on the third layer, and any signal lines can be distributed on the fourth layer. The continuous ground plane layout of the second layer is necessary to establish an RF signal path with controlled impedance. It also facilitates the shortest possible ground loop, and provides a high degree of electrical isolation for the first and third layers, making the two layers The coupling between is minimal. Of course, other board layer definition methods can also be used (especially when the circuit board has a different number of layers), but the above structure is a proven successful example.

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   Figure 2: Capacitor impedance changes at different frequencies


A large area of the power layer can make Vcc wiring easy, but this structure is often a fuse that causes system performance degradation. Connecting all the power leads together on a larger plane will inevitably prevent the pin between the pins. Noise transmission. Conversely, if a star topology is used, the coupling between different power supply pins will be reduced. Figure 1 shows the Vcc wiring scheme for the star connection, which is taken from the evaluation board for the MAX2826 IEEE 802.11a/g transceiver. In the figure, a main Vcc node is established, from which power lines of different branches are drawn to supply power to the power pins of the RF IC. Each power supply pin uses an independent lead to provide spatial isolation between the pins, which is beneficial to reduce the coupling between them. In addition, each lead also has a certain parasitic inductance, which is exactly what we want, and it helps filter out high-frequency noise on the power line.


When using the star topology Vcc lead, it is also necessary to take appropriate power decoupling, and the decoupling capacitor has a certain parasitic inductance. In fact, the capacitor is equivalent to a series-connected RLC circuit. The capacitor plays a leading role in the low frequency band, but at the self-excited oscillation frequency (SRF):


After that, the impedance of the capacitor will appear inductive. It can be seen that the capacitor only has a decoupling effect when the frequency is close to or lower than its SRF, and the capacitor exhibits low resistance at these frequencies. Figure 2 shows the typical S11 parameters under different capacitance values. From these curves, you can clearly see the SRF. It can also be seen that the larger the capacitance, the better the decoupling performance provided at lower frequencies (the greater the impedance presented). Low).


It is best to place a large-capacity capacitor, such as 2.2μF, at the main node of the Vcc star topology. This capacitor has a low SRF, which is very effective for eliminating low-frequency noise and establishing a stable DC voltage. Each power pin of the IC requires a low-capacity capacitor (such as 10nF) to filter out high-frequency noise that may be coupled to the power line. For those power supply pins that supply power to noise-sensitive circuits, two external bypass capacitors may be required. For example: using a 10pF capacitor in parallel with a 10nF capacitor to provide a bypass can provide a wider frequency range of decoupling and try to eliminate the influence of noise on the power supply voltage. Each power supply pin needs to be carefully inspected to determine how much decoupling capacitors are needed and at which frequency points the actual circuit is susceptible to noise interference.


The combination of good power supply decoupling technology with rigorous PCB layout and Vcc leads (star topology) can lay a solid foundation for any RF system design. Although there are other factors that reduce the system performance indicators in the actual design, having a "noise-free" power supply is the basic element for optimizing system performance.


Grounding and via design


The layout and lead of the ground layer are also the key to the design of the WLAN circuit board, they will directly affect the parasitic parameters of the circuit board, and there is a hidden danger of reducing system performance. There is no unique grounding scheme in RF circuit design. There are several ways to achieve satisfactory performance indicators in the design. The ground plane or lead can be divided into analog signal ground and digital signal ground, and it can also isolate circuits with high current or high power consumption. According to the design experience of the WLAN evaluation board in the past, using a separate ground plane in a four-layer board can achieve better results. With these empirical methods, the RF part is isolated from other circuits with a ground layer, which can avoid cross-interference between signals. As mentioned above, the second layer of the circuit board is usually used as a ground plane, and the first layer is used to place components and RF leads.

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 Figure 3: Electrical characteristic model of vias.


After the ground plane is determined, it is very important to connect all signal grounds to the ground plane in the shortest path. Vias are usually used to connect the ground wire of the top layer to the ground plane. It should be noted that the vias are inductive. Figure 3 shows the accurate electrical characteristic model of the via, where Lvia is the via inductance, and Cvia is the parasitic capacitance of the via PCB pad. If you use the ground layout technology discussed here, you can ignore the parasitic capacitance. A 1.6mm deep via hole with a 0.2mm aperture has an inductance of approximately 0.75nH, and the equivalent reactance in the 2.5GHz/5.0GHz WLAN band is approximately 12Ω/24Ω. Therefore, a ground via cannot provide a true ground for the RF signal. For high-quality circuit board designs, as many ground vias as possible should be provided in the RF circuit part, especially for the exposed ground in general IC packages. Pad. Poor grounding will also produce harmful radiation in the receiving front end or power amplifier part, reducing gain and noise figure indicators. It should also be noted that poor soldering of the ground pad can cause the same problem. In addition, the power consumption of the power amplifier also requires multiple vias to connect to the ground plane.

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 Figure 4. PLL filter component layout using the MAX2827 reference design board as an example.


Filter out the noise of other stage circuits and suppress the noise generated locally, thereby eliminating the cross-interference between the stages through the power line, which is the benefit of Vcc decoupling. If the decoupling capacitor uses the same ground via, due to the inductance effect between the via and the ground, the vias at these connection points will carry all the RF interference from the two power supplies, which not only loses the function of the decoupling capacitor, but also It also provides another path for the inter-stage noise coupling in the system.

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As you will see in the latter part of this article, the realization of PLL always faces huge challenges in system design. In order to obtain satisfactory spurious characteristics, it is necessary to have a good ground wire layout. At present, all PLLs and VCOs are integrated into the chip in IC design. Most PLLs use digital current charge pump output to control the VCO through a loop filter. Usually, a second-order or third-order RC loop filter is required to filter the digital pulse current of the charge pump to obtain the analog control voltage. The two capacitors near the output of the charge pump must be directly connected to the ground of the charge pump circuit. In this way, the pulse current path of the ground loop can be isolated, and the corresponding stray frequency in the LO can be minimized. The third capacitor (for the third-order filter) should be directly connected to the ground of the VCO to prevent the control voltage from floating with the digital current. If these principles are violated, considerable spurious components will result.


Figure 4 shows an example of PCB layout. There are many ground vias on the ground pad, allowing each Vcc decoupling capacitor to have its own separate ground via. The circuit in the box is a PLL loop filter. The first capacitor is directly connected to GND_CP, the second capacitor (in series with an R) is rotated 180 degrees to return to the same GND_CP, and the third capacitor is connected to GND_VCO. This kind of grounding scheme can obtain higher system performance.


Suppress PLL spurious signals with proper power and ground


It is a difficult point in the design process to meet the requirements of the 802.11a/b/g system to transmit the spectrum mask. The linearity index and power consumption must be balanced, and a certain margin must be reserved to ensure that it meets the IEEE under the premise of maintaining sufficient transmit power. And FCC regulations. The typical output power required by the IEEE 802.11g system at the antenna end is +15dBm, and the frequency deviation is -28dBr when the frequency deviation is 20MHz. The power rejection ratio (ACPR) of adjacent channels in a frequency band is a function of the linear characteristics of the device, which is correct for a specific application under certain premises. A large amount of work to optimize the ACPR characteristics in the transmission channel is achieved by adjusting the bias of the Tx IC and PA based on experience, and tuning the matching network of the input stage, output stage and intermediate stage of the PA.

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Figure 5: The effect of using a loop filter.


However, not all problems that cause ACPR are attributed to the linear characteristics of the device. A good example is: after a series of adjustments, the power amplifier and the PA driver (two factors that play a major role in ACPR) are optimized. , The adjacent channel characteristics of the WLAN transmitter still cannot reach the expected index. At this time, it should be noted that the spurious signal from the local oscillator (LO) in the transmitter's phase-locked loop will also degrade the ACPR performance. The spurious signal of the LO will be mixed with the modulated baseband signal, and the mixed component will be amplified along the expected signal channel. This mixing effect will only cause problems when the PLL spurious component is higher than a certain threshold. When the PLL spurious component is below a certain threshold, ACPR will be mainly restricted by the PA nonlinearity. When the Tx output power and the spectral mask characteristics are "linearly limited", we need to balance the linearity index and the output power; if the LO spurious characteristics become the main factor restricting the ACPR performance, what we face will be "spurious "Limited", the PA needs to be biased at a higher operating point under the specified POUT to reduce its impact on ACPR, which will consume more current and limit design flexibility.


The above discussion raises another question, that is, how to effectively limit the PLL spurious components within a certain range so that it does not affect the emission spectrum. Once the spurious components are found, the first solution that comes to mind is to narrow the bandwidth of the PLL loop filter in order to attenuate the spurious signal amplitude. This method is effective in rare cases, but it has some potential problems.


Figure 5 shows a hypothetical situation. It is assumed that a divide-by-N synthesizer with a relative frequency of 20MHz is used in the design. If the loop filter is a second-order, the cut-off frequency is 200kHz, and the roll-off rate is usually 40dB/ Decade, 80dB attenuation can be obtained at 20MHz frequency. If the reference spurious component is -40dBc (assuming that the level of harmful modulation components can be caused), the mechanism of generating the spurious may exceed the range of the loop filter (if it is generated before the filter, its amplitude may be very Big). Compressing the bandwidth of the loop filter will not improve the spurious characteristics, but will increase the PLL lock time, which will have a significant negative impact on the system.


Experience has proved that the most effective way to suppress PLL spurs should be reasonable grounding, power supply layout and decoupling technology. The wiring principles discussed in this article are a good design start to reduce PLL stray components. Considering that there is a large current change in the charge pump, it is very necessary to adopt a star topology. If there is not enough isolation, the noise generated by the current pulse will be coupled to the VCO's power supply and modulate the VCO frequency, which is usually called "VCO traction". Measures such as physical separation between power lines and decoupling capacitors for each Vcc pin, reasonable placement of grounding vias, and introduction of a series ferrite component (as a last resort) can improve isolation. The above measures do not need to be used in every design. Appropriate use of each method will effectively reduce the spurious amplitude.


Figure 6 provides a result of an unreasonable VCO power supply decoupling scheme. The power supply ripple shows that it is the switching effect of the charge pump that causes strong interference on the power line. Fortunately, this strong interference can be effectively suppressed by adding bypass capacitors. In addition, if the power supply wiring is unreasonable, for example, the power lead of the VCO is located just below the charge pump power supply, the same noise can be observed on the VCO power supply, and the generated spurious signals are enough to affect the ACPR characteristics, even if the decoupling is strengthened, the test The result will not be improved. In this case, it is necessary to examine the PCB wiring and rearrange the power supply leads of the VCO, which will effectively improve the stray characteristics and meet the specifications required by the specification.

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Figure 6: Unreasonable VCC_VCO decoupling test results