PCB Tech - Engineer's summary: PROTEL technology encyclopedia (Two)

1. Parasitic capacitance of vias

The via itself has a parasitic capacitance to the ground. If it is known that the diameter of the isolation hole on the ground layer of the via is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, then the parasitic capacitance of the via is approximately:

C=1.41εTD1/(D2-D1)

The main effect of the parasitic capacitance of the via on the circuit is to extend the rise time of the signal and reduce the speed of the circuit. For example, for a PCB with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, then we can approximate the via using the above formula The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF, the rise time change caused by this part of the capacitance is: T10-90=2.2C(Z0/2)=2.2 x0.517x(55/2)=31.28ps. It can be seen from these values that although the effect of the rise delay caused by the parasitic capacitance of a single via is not obvious, if the via is used multiple times in the trace to switch between layers, the designer should still consider carefully.

Second, the parasitic inductance of the via

Similarly, there are parasitic capacitances along with vias. In the design of high-speed digital circuits, the damage caused by the parasitic inductance of the vias is often greater than the impact of the parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can simply calculate the parasitic inductance of a via with the following formula:

L=5.08h[ln(4h/d)+1] where L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center hole. It can be seen from the formula that the diameter of the via has a small influence on the inductance, and the length of the via has the greatest influence on the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is: XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when high-frequency currents pass. Special attention should be paid to the fact that the bypass capacitor needs to pass through two vias when connecting the power plane and the ground plane, so that the parasitic inductance of the vias will increase exponentially.

3. Via design in high-speed PCB

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering the cost and signal quality, choose a reasonable size via size. (E.g. for floors 6-10)

For memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil vias. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the vias

3. Try not to change the layers of the signal traces on the PCB board, that is to say, try not to use unnecessary vias.

4. The pins of the power supply and the ground should be punched nearby, and the lead between the vias and the pins should be as short as possible, because they will

Lead to an increase in inductance. At the same time, the power and ground leads should be as thick as possible to reduce impedance.

5. Place some grounded vias near the vias of the signal layer to provide the nearest loop for the signal. It is even possible to place a large number of redundant ground vias on the PCB board. Of course, the design needs to be flexible. The via model discussed earlier is the case where there are pads on each layer. Sometimes, we can reduce or even remove the pads of some layers. Especially when the density of vias is very high, it may lead to the formation of a break groove that separates the loop in the copper layer. To solve this problem, in addition to moving the position of the via, we can also consider placing the via on the copper layer. The pad size is reduced.

Question: Why can’t the symbols copied from the WORD file be displayed normally in PROTEL?

Reply: Are you in the SCH environment or the PCB environment? There are some special characters that cannot be displayed in the PCB environment because the words are reserved at that time.

Question: The net name is the same as the port name, can it be connected in PCB?

Answer: Yes, PROTEL can generate networks in multiple ways. When you use port-port in the hierarchical diagram, each circuit diagram can use the same NET name, and they will not be connected because the network name is the same. But please don’t Use the power port because that is global.

Question: Why is the pad property changed when I import the PADS file in PROTEL99SE?

Fu: This is mostly caused by the differences between the two software and each version, usually just a manual adjustment.

Question: May I ask Yang Daxia: Why can't I modify the properties in Protel after converting the power logic schematic diagram into Protel through software. If I modify it, it is either unrealistic or full display properties? Thank you!

Complex: If display all, you can make a global edit, and only display the desired part.

Question: What are the principles of copper paving?

Complex: Copper should generally be laid at more than 2 times your safety distance. This is the general knowledge of LAYOUT.' d: W4 k: b# W* G5 i) E

Question: Is there any improvement in the automatic layout of Potel DXP? Can it be automatically arranged according to the layout of the schematic when importing the package? # b" _1 n3 q7 J- V( Q8 N: w

Re: PCB layout and schematic layout are not necessarily inherently related. Therefore, Potel DXP will not automatically arrange the layout according to the schematic layout during automatic layout. (The component classes established according to the sub-diagram can help the PCB layout to be connected according to the schematic diagram).

Question: Where can I buy the data for signal integrity analysis?

Re: Protel software is equipped with a detailed signal integrity analysis manual.

Question: Why is the copper paved? How big is the file? Is there any way?

Complex: The amount of copper-plated data is understandable. But if it is too large, your settings may be unscientific.

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Q: Is there any way to make the graphic symbols of the schematic diagram zoomable?

Re: No.

Question: PROTEL simulation can be used for principle demonstration, and good results can be obtained if there is a detailed model

Complex: PROTEL simulation is fully compatible with Spice models. Free Spice models can be obtained from device manufacturers for simulation. PROTEL also provides modeling methods, has professional simulation knowledge, and can build effective models.

Question: How to add Chinese characters in 99SE, if it seems that a lot of things are missing after Sinicization! 3-28 14:17:0 But it does lack a lot of features!

Fu: It may be that the Chinese version is wrong.

Question: How to make a pad with a hole of 2*4MM and an outer diameter of 6MM?

Complex: Mark the square hole size on the mechanical layer. Communicate specific requirements with the plate maker.

Question: I know, but how to connect the power and ground to the inner layer. There is no network table, if there is a network table, there is no problem 4 X* ^! S. c/ {

Complex: Use the from-to class to generate network connections

Question: I would like to ask how to make the oval pad in 99se? The method of placing continuous pads is not advisable, and the circuit board manufacturers are not happy. Can I add this setting item in the next version?

Complex: When building library components, you can use non-pad pixels to form the desired pad shape. Make it have the same network attributes during PCB design. We can advise Protel.

Question: How to get the previous principle library and PCB library for free

Reply: Then you can download it from WWW.PROTEL.COM

Question: I just mentioned how to write hollow (not copper-clad) text on the copper-clad. The expert replied that it was written first, then the copper-clad, and then the words were deleted. However, I tried it, and after deleting the words, the words were not empty., Is covered by copper, may I ask the experts if they are mistaken, can you give it a try?

Re: The word must use the method of placing Chinese provided by PROTEL99SE, and then remove the Chinese (English) word from the component, (because it is a component), set the safety gap to 1MIL, then pour the copper, and then move the copper. The program will ask if Re-cover the copper and answer NO.

Question: When drawing a schematic diagram, what is the pin order of the components?

Complex: When building a schematic library, there is a powerful check function, which can check serial numbers, duplicates, omissions, etc. You can also use the array layout function to place regular pins at one time.

Question: After protel99se6 is automatically wired, there will be messy wiring near the pins of the integrated block, like burrs, and sometimes even triangular wiring, which requires a lot of manual correction. How to avoid this problem?

Complex: Set the component grid reasonably and optimize the routing again.

Question: I used PROTEL to draw a picture, and after repeated revisions, it was found that the file size was very large (swollen), and it was much smaller after exporting and then importing it. Why? ? Are there other ways to slim down the file?

Fu: Actually, at that time, the copper paving of PROTEL was caused by the composition of the lines. Due to intellectual property issues, the "watering" function in PADS could not be used, but it has its advantage, that is, it can automatically delete the "dead copper". Since the file is large, you can compress it with WINZIP and it will be very small. Will not affect your file delivery.

Question: Excuse me: on the same wire, how to make different parts of it have different widths and look continuous and beautiful? Thank you!

Re: Can't be done automatically, you can use editing skills to achieve it.

Liaohm asked: How to divide a circular arc into several equal parts?

Fanglin163 replied: Use conventional geometric knowledge. EDA is just a tool.

Question: The HDL used in Protel is ordinary VHDL

Complex: Protel PLD is not, Protel FPGA is.

Question: After the teardrops are filled, the copper is laid. Sometimes the grids will be incomplete. What should I do?

Fu: That's because you set up a thermal isolation zone when filling teardrops. You only need to pay attention to the safety distance and the thermal isolation zone. It can also be repaired.

Q: Is it possible to make asymmetrical pads? When dragging the wiring, the connected lines keep the original angle and drag together?

Complex: Asymmetrical pads can be made. When dragging the wiring, the connected lines cannot be dragged together at the original angle.

Question: Will Protel achieve the same effect as high-end EDA software when it reaches the end of the day)

Complex: It depends on the design.

Question: Can the automatic wiring effect of Protel DXP reach the level of the original ACCEL?

Re: There is nothing worse than the past.

Q: Protel's pld function does not seem to support the popular HDL language?

Re: The Cupl language used by Protel PLD is also a HDL language. The next version can be input directly in VHDL language.

Q: What are the hardware requirements for the 3D function in the PCB?

Complex: Need to support OpenGL.1

Question: How to put the wiring of a physical hard plate into the computer quickly and intact?

Re: The fastest way is to scan, then use the BMP2PCB program to convert into a film file, and then modify, but your PCB accuracy must be above 0.2MM. The BMP2PCB program can be downloaded on 21IC, your circuit board must be very bright with sandpaper to be successful.

Question: How to define the network name for a circuit contact when drawing the PCB directly?

Re: set in the Net edit dialog box. )

Question: How to make the aperture display or symbol mark in the data made, the same as allego

Complex: There are options in the output, which can generate drill statistics and various aperture symbols.

Question: The locking function of automatic wiring is not easy to use, and some systems will be re-distributed. I don't know what's going on?

Re: The latest version has no such problems.

Question: How to realize the overall flip of multiple original devices

Duplicate: Select the component you want to flip at one time.

Question: The p 99 version I use crashes after adding Chinese characters. What is the reason?

Re: It should be caused by version D.

Question: How to open the file of powpcb with PROTEL?

Re: Create a new PCB file first, and then use the import function to reach it.

Question: How to import GERBER file from PROTEL99

Re: Protel PCB can only import its own Gerber, while Protel's CAM can import Gerber in other formats.

Question: How to partially change the thin lines of the PCB traces to thick lines

Re: Double-click to modify + global editing. Pay attention to the matching conditions. Modify the rules to adapt to the new line width.

Q: How to modify the pad size in an integrated circuit package? How to set it if it is modified globally?

Duplicate: select all for global editing

Q: How to modify the pad size in an integrated circuit package?

Complex: Modify the pad size in an integrated circuit package in the library, as everyone knows, it can also be modified on the PCB board. (First unlock in the component properties). "

Question: Can some parts of the component symbols be modified or deleted when making the PCB?

Complex: Remove the component lock in the component properties, you can edit the component in the PCB, and will not affect the component in the library.

Question: The pad is a ground wire. After the ground is covered, how to set the width of the connection between the pad and the ground

Complex: Set the connection method with the pad before wrapping the ground

Question: Why should 99se be changed to the project format when storing?