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Integrated transceiver simplifies design and improves phased array radar performance
2021-09-14
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Author:Frank

The phased array radar system has multiple transmitting and receiving channels. Previously, these systems were constructed using separate transmit and ICreceive chips (IC). These systems use separate chips in the digital-to-analog converter (DAC) of the transmitting PCB circuit and the analog-to-digital converter(ADC) of the receiving (Rx) circuit, respectively. This discrete solution makes many systems large in size, costly, and high in power consumption, so that the required number of channels can be obtained to perform the required functions. Due to the complex manufacturing and calibration processes, these systems usually take a long time to market. However, a method using integrated transceivers has recently emerged, which merges many functions that were once considered completely different into a single IC. These ICs help to achieve a phased array radar system with small size, low power consumption and low cost, high channel count, and a shorter time to market.

The integrated transceiver integrates multiple functions into a single IC, such as ADI's ADRV9009 transceiver (Figure 1). It integrates DAC, ADC, local oscillator (LO) frequency synthesizer, microprocessor, mixer and more functions into a 12mm×12mm single chip. In addition, the product also integrates two receiving channels and two transmitting channels as well as multiple digital signal processing (DSP) components to obtain the instantaneous bandwidth required by the system. An application programming interface (API) is also provided for operating the transceiver on the customer's software platform. The on-chip front-end network can be used to achieve gain and attenuation control. Built-in initialization and tracking calibration routines are used to provide the performance required for many communications and military applications.


These integrated transceivers can create all the clock signals required by the transmitter and receiver by injecting a reference clock signal called REF_CLK. Then, all the clocks required for DAC/ADC sampling, LO generation, and microprocessor clock are synthesized by the on-chip phase-locked loop (PLL). If the internal LO phase noise is not enough to meet the customer's application requirements, the user can inject a low phase noise LO from the outside.

The data from the transceiver is transmitted via the standardized JESD204b high-speed serial data interface. This interface supports receiving and sending large amounts of data at the same time. The new integrated transceiver solution can help provide interface IP and help customers speed up time to market. If deterministic delay and data synchronization are required, users can use the built-in multi-chip synchronization (MCS) feature and send the SYS_REF signal as the main timing reference for the initial channel alignment sequence (ILAS)1.

In addition, the built-in RFPLL phase synchronization feature can be used to set the LO phase of the transmit or receive channel to be deterministic relative to the main reference phase. By using the MCS and RFPLL phase synchronization characteristics, you can ensure phase alignment when initializing components, frequency tuning, or opening/closing the transceiver channel. Figure 2 shows an example of a new integrated transceiver that provides deterministic phase and supports all of these features.

Figure 2: The built-in RFPLL phase synchronization feature allows a deterministic phase relationship between the system and the main reference source.

Use multiple integrated transceivers
If the system requires more than two receivers and two transmitters, users can still use multiple integrated transceivers and benefit from the small size achieved by the single-chip receive and transmit channels. An example of this technique is shown in Figure 3. The internal frequency divider of all ICs can be triggered at the same time by using the concurrent SYS_REF pulse to synchronize multiple integrated transceivers. These SYS_REF pulses can be issued by a clock chip or a baseband processor with a programmable delay, which can compensate for delay fluctuations caused by mismatched path lengths between ICs. As a result, data paths across multiple chips and multiple LOs can be deterministically delayed.

Figure 3: Multiple integrated transceivers can be used to increase the number of channels in the system.

Integrated transceiver is the backbone of phased array radar
By using synchronous integrated transceivers to increase the number of channels, these devices become the backbone of the phased array radar platform. When combined with phase and amplitude aligned transmit and receive channels, the use of multiple integrated transceivers can improve system-level dynamic range, spurious, and phase noise.

On-chip DSP features, such as numerically controlled oscillator (NCO) and digital up-converter or digital down-converter (DDC), now support the use of system-level spurious decorrelation methods within a single IC2.

By using multiple integrated transceivers to combine transceiver channels, system-level noise spectral density (NSD) and spurious performance are improved. This move improves the dynamic range of the phased array radar system by reducing the effective background noise of the system while maintaining all the functions of the channel. Figure 4 shows the system-level measurement results obtained after integrating up to 8 integrated transceiver receiving channels and effectively increasing the number of bits in the phased array system. Note that when increasing from one channel to eight channels, the NSD and the calculated noise floor (represented by the red line in each figure) will increase by 6 dB. This is because, although there are a total of 8 channels, there are only 4 different and unrelated LOs (NLO = 4) among the 4 integrated transceivers used to create these 8 channels. Therefore, the following improvements have been achieved:

The results obtained are similar to the experimental results provided by the integrated transceiver. In addition, redundant imaging frequencies are aggregated in an uncorrelated manner to achieve system-level spurious performance improvement. As the number of channels increases, the performance will be further improved to achieve a scalable system.

Figure 4: Using the ADRV9009 integrated transceiver to integrate the receive channel can reduce the noise spectral density and improve the dynamic range.

In addition, after aligning the phase and integrating multiple integrated transceiver channels, the phase noise of the phased array system can be improved. From the measurement results shown in the top three curves of Figure 5, it can be seen that the phase noise performance is improved after 8 channels are combined using the internal LO of 4 integrated transceiver ICs. To repeat it again, when there are 4 different and uncorrelated LOs, when increasing from 1 transmission channel to 8 transmission channels, the phase noise will increase by 6dB. Increasing the number of channels will further increase the phase noise of the phased array radar system. Alternatively, an external LO can be injected into each sub-array composed of N TRx integrated transceivers, and the initial phase noise can be improved from the sub-array level (as shown by the blue curve in Figure 5). However, in this way, since the elements in the sub-array all share the same LO source, they are related to each other, so it is impossible to provide channel aggregation improvement in the sub-array by themselves. For the external LO phase noise data shown in Figure 5, an R&S SMA100B signal generator is used as an external LO source.

Figure 5: When using internal LO, integrating multiple ADRV9009 transmit channels can improve system-level phase noise performance. Injecting an external LO will improve the initial phase noise of the sub-array.

Integrated DSP features (such as NCO, digital phase shifter, and DUC/DDC) allow the implementation of baseband phase shift and frequency shift in the digital domain, which in turn allows the implementation of digital beams in multi-channel, integrated transceiver-based phased array radar systems Shaping. After integrating multiple functions into a single IC, the system can now use integrated transceivers to achieve antenna lattice spacing in many related phased array applications. Using more transceivers to increase the number of channels can generally narrow the beam, but will result in a larger system. However, now that multiple functions are integrated into a single IC, the proportion of the system becoming larger is still smaller than in the past. After using MATLAB® to simulate the radiation pattern, Figure 6 shows how the beam narrows when the number of channels is increased from 8 to 1024, and how the theoretical lobe amplitude becomes deeper. The actual power zero point will be determined in the antenna design.


in conclusion
Integrating multiple digital and analog functions in a single IC can realize a smaller phased array radar system. These systems support the implementation of digital beamforming and hybrid beamforming, depending on the system specifications. It has been proven that system-level performance improvements can be achieved using ADI's ADRV9009. These integrated devices allow many new systems to use the same hardware to run multiple applications.