PCB Tech - Synchronous switching noise of FPGA on PCB

Nowadays, CMOS technology allows an FPGA device to have multiple I/O interfaces. At the same time, in recent years, low power consumption has begun to become the mainstream concept of high-speed I/O interfaces. The most effective way to reduce power consumption is to reduce the voltage, and the voltage reduction will result in a smaller noise margin allowed by the I/O interface. Therefore, it is very necessary for FPGA users to quantify the system-level synchronous switching noise (SSN) in the chip, package, and PCB environment.

This article systematically introduces SSN, focusing on SSN caused by FPGA output buffering. This kind of noise is generally called Synchronous Switching Output Noise (SSO), which is different from SSN caused by input buffering. This article introduces the causes of system-level SSO, and proposes a layered system-level SSO modeling method. At the same time, this article also explains how to associate the SSO model with frequency domain and time domain measurements, and gives several PCB design methods to reduce SSO.

The formation mechanism of system-level SSO

A PCB with FPGA is a complex system that can be divided into a chip part containing active circuits, a package part with embedded passive components supporting traces, and a circuit board part that provides connections between the FPGA and the outside. In this type of system, it is difficult to understand the noise characteristics inside the chip. Therefore, it is very valuable to quantify the SSO at the near and far ends of the PCB traces connected to the FPGA. There are two main factors that cause SSO: the impedance of the power distribution network (PDN) and the mutual inductance coupling between the switch I/O.

From a system perspective, PDN includes wafer-level, package-level, and board-level components, which together provide power for CMOS circuits. When a certain number of CMOS output drive circuits are turned on at the same time, a large current will flow into the inductive circuit elements of the PDN instantaneously, resulting in a delta-I voltage drop. Interconnect structures generate parasitic inductances, such as power solder balls on the ball grid array package and power vias in the PCB. This rapidly changing current also excites radial electromagnetic waves between the power/ground plane pair. The electromagnetic waves are reflected from the planar edge of the PCB, creating resonance between the power/ground plane, and causing voltage fluctuations.

Another important cause of SSO is mutual inductance coupling, especially the mutual inductance coupling around the chip package/PCB edge. The solder balls on the chip BGA package and the vias on the PCB belong to a tightly coupled multi-wire structure. Each I/O solder ball and its corresponding PCB via and its nearest ground solder ball and ground via form a closed loop. When the state of multiple I/O ports changes at the same time, transient I/O currents flow through these signal loops. This transient I/O current will generate a time-varying magnetic field, which invades adjacent signal loops and causes induced voltage noise.

An excellent SSO model should be able to reflect the basic formation mechanism of SSO. A layered model for predicting SSO in PCBs. At the chip level, what we need is an output buffer model that can provide accurate current distribution on power lines and signal lines with limited complexity. At the packaging level, for simplicity, modeling tools can be used to obtain the PDN model and the signal coupling model, but the interaction between the PDN and the signal coupling model should be carefully considered. These two models act as a bridge, connecting the output buffer model at the bump end of the chip package and the PCB-level model at the solder ball end. The PDN model of the PCB usually includes the power/ground plane and the large-capacity/decoupling capacitors on it, while the signal coupling model of the PCB includes a tightly coupled via array and loosely coupled signal traces on different signal layers. The interaction effect of these two PCB-level models appears in the PCB via array. It is from here that inductive crosstalk brings noise into the PDN model, and delta-I noise in turn reduces the quality of the I/O signal. This hierarchical modeling method maintains the simulation accuracy reasonably, and at the same time improves the computational efficiency of such complex systems.