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Introduction and analysis of new microelectronic packaging technology
2021-08-19
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Author:IPCB

1 Introduction


The circuit industry has become the key to the development of the national economy, and integrated circuit design, manufacturing, and packaging and testing are the three pillars of the integrated circuit industry. This is the consensus of leaders at all levels and the industry. Microelectronic packaging not only directly affects the electrical, mechanical, optical, and thermal performance of the integrated circuit itself, but also affects its reliability and cost. It also determines the miniaturization, multi-function, and Reliability and cost, microelectronic packaging is getting more and more attention from people, and it is in a stage of vigorous development both at home and abroad. This article attempts to review the rapid development of new microelectronic packaging technologies since the 1990s, including ball array packaging (BGA), chip size packaging (CSP), wafer level packaging (WLP), three-dimensional packaging (3D) and System packaging (SIP) and other technologies. Introduce their development status and technical characteristics. At the same time, the concept of microelectronics three-level packaging is described. And put forward some thoughts and suggestions for the development of my country's new microelectronic packaging technology. This article attempts to review the rapid development of new microelectronic packaging technologies since the 1990s, including ball array packaging (BGA), chip size packaging (CSP), wafer level packaging (WLP), three-dimensional packaging (3D) and System packaging (SIP) and other technologies. Introduce their development status and technical characteristics. At the same time, the concept of microelectronics three-level packaging is described. And put forward some thoughts and suggestions for the development of my country's new microelectronic packaging technology.


  2 Microelectronics three-level packaging


For microelectronics packaging, we must first describe the concept of three-level packaging. Generally speaking, microelectronic packaging is divided into three levels. The so-called first-level packaging is to encapsulate one or more integrated circuit chips in a suitable packaging form after the semiconductor wafer is split, and use wire bonding (WB) and carrier tape for the welding area of the chip and the external pins of the package. Automatic bonding (TAB) and flip chip bonding (FCB) are connected to make them become electronic components or assemblies with practical functions. The first-level package includes two categories: single-chip module (SCM) and multi-chip module (MCM). The third-level packaging is to connect the second-level packaged products with the motherboard through layer selection, interconnect sockets or flexible circuit boards to form a three-dimensional package to form a complete system. This level of packaging should include connectors and laminates Assembling and flexible circuit boards and other related materials, design and assembly technology. This level is also called system-in-package. The so-called microelectronics package is an overall concept, including all technical content from one-pole packaging to three-pole packaging. We should bring our existing knowledge into the track of international microelectronic packaging, which will not only benefit the technical exchanges between my country's microelectronic packaging industry and foreign countries, but also the development of my country's microelectronic packaging itself.


  3 New microelectronic packaging technology


The history of integrated circuit packaging is divided into three stages. The first stage, before the 1970s, was mainly cartridge type packaging. Including the original metal circular (TO type) package, later ceramic dual in-line package (CDIP), ceramic-glass dual in-line package (CerDIP) and plastic dual in-line package (PDIP). In particular, PDIP has become a mainstream product due to its excellent performance, low cost and mass production. In the second stage, after the 1980s, the surface mount type four-side lead package was the main one. At that time, the surface mount technology was called a revolution in the field of electronic packaging, and it developed rapidly. Correspondingly, a number of packaging forms adapted to surface mount technology, such as plastic leaded chip package (PLCC), plastic quad flat package (PQFP), plastic small outline package (PSOP), and leadless quad flat package, etc. The packaging form came into being and developed rapidly. Due to high density, small lead pitch, low cost and suitable for surface mounting, PQFP became the leading product in this period. The third stage, after the 1990s, was mainly in the form of area array packaging. Thin film multilayer substrate MCM (MCM-D), plastic multilayer printed circuit board MCM (MCM-L) and thick film substrate MCM (MCM-C/D).


3.13D package


There are three main types of 3D packaging, namely buried 3D packaging. There are currently three main ways: one is to "embed" R, C or IC components in various substrates or multilayer wiring dielectric layers, and then the top layer Mounting SMC and SMD to achieve three-dimensional packaging, this structure is called embedded 3D packaging; the second is to implement multi-layer wiring on the active substrate after silicon wafer scale integration (WSl), and then mount the top layer SMC and SMD form a three-dimensional package. This structure is called an active substrate type 3D package; the third type is based on the 2D package by stacking multiple bare chips, packaged chips, multi-chip components and even wafers. Interconnect to form a three-dimensional package. This structure is called a stacked 3D package. Among these 3D packaging types, the fastest growing is stacked bare chip packaging. There are two reasons. First, the huge market for mobile phones and other consumer products requires that the package thickness be reduced while increasing functions. The second is that the process it uses is basically compatible with the traditional process, and it can be mass-produced and put on the market soon after improvement. According to Prismarks forecast, the world's mobile phone sales will increase from 393M in 2001 to 785M-1140M in 2006. The annual growth rate reaches 15-24%. Therefore, it is estimated on this basis that stacked bare chip packaging will grow at a rate of 50-60% from now to 2006. Figure 6 shows the appearance of the stacked bare chip package. Its current level and development trend are shown in Table 3.


There are two stacking methods for stacked bare chip packaging. One is the pyramid type, where the size of the bare chip is getting smaller and smaller from the bottom layer; the other is the cantilever type, where the size of the stacked chip is the same. In the initial stage of application to mobile phones, stacked bare chip packaging was mainly to stack FlashMemory and SRAM together. Currently, FlashMemory, DRAM, logic IC, and analog IC can be stacked together. The key technologies involved in stacked bare chip packaging are as follows. ① Wafer thinning technology, as mobile phones and other products require thinner and thinner packaging, the current packaging thickness is required to be below 1.2mm or even 1.0mm. The number of stacked chips continues to increase, so the chips must be thinned. The methods of wafer thinning include mechanical grinding, chemical etching or ADP (Atmosphere Downstream Plasma). Mechanical grinding thinning is generally about 150μm. The plasma etching method can reach 100μm, and the thinning of 75-50μm is under development; ②Low arc bonding, because the chip thickness is less than 150μm, the high bonding arc must be less than 150μm. At present, the normal bonding arc height of 25μm gold wire is 125μm, but after the reverse wire bonding optimization process, the arc height can reach 75μm or less. At the same time, the reverse wire bonding technology needs to add a bending process to ensure the gap between the different bonding layers; ③The wire bonding technology on the cantilever beam, the longer the cantilever beam, the greater the chip deformation during bonding, and the design and optimization must be optimized. Process; ④ Wafer bump production technology; ⑤ No-swing (NOSWEEP) molding technology for bonding wires. Due to the higher bonding wire density, longer length and more complex shape, the possibility of short circuits is increased. Using a low-viscosity molding compound and reducing the transfer speed of the molding compound helps to reduce the swing of the bonding wire. At present, the bonding wire no-swing (NOSWEEP) molding technology has been invented.

ATL

  3.2 Ball Array Package (BGA)


Package Array (BGA) is a new type of package developed in the early 1990s in the world.


The I/O terminals of the BGA package are distributed under the package in the form of circular or columnar solder joints. The advantage of BGA technology is that although the number of I/O pins has increased, the pin spacing has not decreased but increased. Improves the assembly yield; although its power consumption increases, BGA can be welded with a controlled collapse chip method, which can improve its electrothermal performance; thickness and weight are reduced compared with previous packaging technology; parasitic parameters are reduced, The signal transmission delay is small, and the frequency of use is greatly improved; the assembly can be coplanar welding, and the reliability is high.


The outstanding advantages of this kind of BGA: ①Better electrical performance: BGA uses solder balls instead of leads, leading to a short lead path, reducing pin delay, resistance, capacitance and inductance; ②The packaging density is higher; because the solder balls are arranged on the entire plane , So for the same area, the number of pins is higher. For example, a BGA with a side length of 31mm has 900 pins when the solder ball pitch is 1mm. In contrast, a QFP with a side length of 32mm and a pin pitch of 0.5mm has only 208 pins; ③BGA section The distances are 1.5mm, 1.27mm, 1.0mm, 0.8mm, 0.65mm and 0.5mm, which are fully compatible with the existing surface mounting technology and equipment, and the installation is more reliable; ④The surface tension when the solder melts is "self-aligned" "Effect, avoiding the loss of traditional package lead deformation, greatly improving the assembly yield; ⑤BGA pins are firm and easy to transfer; ⑥The solder ball lead form is also suitable for multi-chip components and system packaging. Therefore, BGA has been explosively developed. BGA due to different substrate materials include plastic ball array package (PBGA), ceramic ball array package (CBGA), carrier tape ball array package (TBGA), heat sink ball array package (EBGA), metal ball array Package (MBGA), as well as Flip Chip Ball Array Package (FCBGA. PQFP can be applied to surface mounting, which is its main advantage. But when the lead pitch of PQFP reaches 0.5mm, its assembly technology is complicated Will increase. In applications where the number of leads is greater than 200 and the package size exceeds 28mm square, BGA packaging is inevitable to replace PQFP. Among the above types of BGA packages, FCBGA has the most hope to become the fastest growing BGA package , Let’s take it as an example to describe the process technology and materials of BGA. In addition to all the advantages of BGA, FCBGA also has: ①Excellent thermal performance, and a heat sink can be installed on the back of the chip; ②High reliability, due to the filler under the chip The function of FCBGA greatly enhances the fatigue life of FCBGA; ③It has strong reworkability.


Because other components are already installed on the surface assembly board, a special small template for BGA must be used. The thickness of the template and the size of the opening must be determined according to the ball diameter and ball distance. After printing, the printing quality must be checked. If it is unqualified, the PCB must be cleaned. Reprint after clean and dry. For CSP with a ball pitch of 0.4mm or less, no solder paste is required, so there is no need to process a template for rework, and paste flux is directly applied to the PCB pad. Put the PCB that needs to be removed into the soldering furnace, press the reflow button, and wait for the machine to finish according to the set program, press the in and out button when the temperature is highest, and use the vacuum suction pen to remove the components to be removed, PCB The plate can be cooled.


The key technologies involved in FCBGA include chip bump manufacturing technology, flip chip bonding technology, multilayer printed board manufacturing technology (including multilayer ceramic substrates and BT resin substrates), chip underfill technology, solder ball attachment technology, and heat dissipation Board attachment technology, etc. The packaging materials it involves mainly include the following categories. Bump materials: Au, PbSn and AuSn, etc.; underbump metallization materials: Al/Niv/Cu, Ti/Ni/Cu or Ti/W/Au; soldering materials: PbSn solder, lead-free solder; multilayer substrate materials : High temperature co-fired ceramic substrate (HTCC), low temperature co-fired ceramic substrate (LTCC), BT resin substrate; underfill material: liquid resin; thermal conductive glue: silicone resin; heat sink: copper.


  3.3 Chip Size Package (CSP)


CSP (Chip Scale Package) package means chip scale package. The latest generation of memory chip packaging technology for CSP packaging has improved its technical performance. CSP package CSP package can make the ratio of chip area to package area exceed 1:1.14, which is quite close to the ideal situation of 1:1. The absolute size is only 32 square millimeters, which is about 1/3 of the ordinary BGA, which is only equivalent. It is 1/6 of the TSOP memory chip area. Compared with the BGA package, the CSP package can increase the storage capacity by three times under the same space.


Chip size package (CSP) and BGA are products of the same era, and are the result of miniaturization and portability of the whole machine. The American JEDEC definition of CSP is: LSI chip package area less than or equal to 120% of the LSI chip area is called CSP. Because many CSPs adopt the form of BGA, the packaging industry authorities in the last two years believe that the solder ball pitch is greater than or equal to 1mm as BGA, and less than 1mm is CSP. Because CSP has more prominent advantages: ①Ultra-small package with approximate chip size; ②Protection of bare chips; ③Excellent electrical and thermal properties; ④High packaging density; ⑤Easy for testing and aging; ⑥Easy for soldering, installation and repair and replacement. Therefore, in the mid-1990s, there was a large-span development, with an annual growth rate of about doubling. Since CSP is in a stage of vigorous development, its types are limited. Such as rigid substrate CSP, flexible substrate CSP, lead frame type CSP, micro molding type CSP, land array CSP, micro BGA, bump chip carrier (BCC), QFN type CSP, chip stack type CSP and wafer-level CSP (WLCSP) etc. The lead pitch of CSP is generally below 1.0mm, including 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm and 0.25mm. Table 2 shows the CSP series.


Generally, CSP cuts the wafer into a single IC chip and then implements the back-end packaging, while WLCSP is different. All or most of its process steps are completed on the silicon wafer that has completed the previous process, and finally The wafer is directly cut into separate independent devices. So this kind of package is also called wafer level package (WLP). Therefore, in addition to the common advantages of CSP, it also has unique advantages: ①The packaging processing efficiency is high, and multiple wafers can be processed at the same time; ②It has the advantages of flip-chip packaging, that is, light, thin, short, and small; ③and Compared with the previous process, only the two processes of pin rewiring (RDL) and bump production are added, and the rest are all traditional processes; ④reduction of multiple tests in traditional packaging. Therefore, the world's large IC packaging companies have invested in the research, development and production of this type of WLCSP. The disadvantage of WLCSP is that the current pin count is low, there is no standardization, and the cost is high.


The center pin form of the CSP packaged memory chip effectively shortens the signal conduction distance, and its attenuation is reduced accordingly. The anti-interference and anti-noise performance of the chip can also be greatly improved, which also makes the access time of CSP 15 better than BGA %-20%. In the CSP packaging method, the memory particles are soldered on the PCB board by solder balls. Due to the large contact area between the solder joints and the PCB board, the heat generated by the memory chip during operation can be easily transferred to the PCB. On the board and radiate out. CSP package can be viewed from the backHeat dissipation and good thermal efficiency. The thermal resistance of CSP is 35°C/W, while the thermal resistance of TSOP is 40°C/W.


CSP technology was proposed during the upgrading of electronic products. Its purpose is to use large chips (chips with more functions, better performance, and more complex chips) to replace the previous small chips. Its package occupies the printed board. The area remains the same or smaller. It is precisely because of the small and thin package of CSP products that it has quickly gained application in handheld mobile electronic devices. In August 1996, Japan's Sharp Corporation began mass production of CSP products; in September 1996, Japan's Sony Corporation began to assemble cameras with CSP products provided by Japan's TI and NEC Corporation; in 1997, the United States also began to produce CSP products . There are dozens of companies in the world that can provide CSP products, and there are more than one hundred varieties of CSP products. [


In addition to the metal deposition technology, photolithography technology, etching technology, etc., the key technologies involved in WLCSP also include rewiring (RDL) technology and bump production technology. Usually the lead-out pads on the chip are arranged on the square aluminum layer around the die. In order to adapt the WLP to the wider pad pitch of the SMT second-level package, these pads need to be redistributed so that these pads are separated by The peripheral arrangement of the chip is changed to the array arrangement on the active surface of the chip, which requires rewiring (RDL) technology. The solder bump manufacturing technology can use electroplating, electroless plating, evaporation, ball placement and solder paste printing. At present, the electroplating method is still the most widespread, followed by the solder paste printing method. The UBM material in the rewiring is Al/Niv/Cu, T1/Cu/Ni or Ti/W/Au. The dielectric materials used are photosensitive BCB (benzocyclobutene) or PI (polyimide) bump materials such as Au, PbSn, AuSn, In, etc.


  3.4 System Package (SIP)


There are usually two ways to realize the functions of an electronic complete system. One is Systemon Chip, or SOC for short. That is, the function of the electronic complete system is realized on a single chip; the other is System-in-Package (SysteminPackage), referred to as SIP. That is, the functions of the whole system are realized through packaging. Academically speaking, these are two technical routes, just like monolithic integrated circuits and hybrid integrated circuits, each has its own advantages and each has its own application market. Both technology and application are complementary. The author believes that SOC should be mainly used for high-performance products with a long application cycle, while SIP is mainly used for consumer products with a short application cycle.


An important feature of SIP is that it does not define the type of session to be established, but only defines how the session should be managed. With this flexibility, it means that SIP can be used in many applications and services, including interactive games, music and video on demand, as well as voice, video, and Web conferencing. SIP messages are text-based, so they are easy to read and debug. The programming of the new service is simpler and more intuitive for designers. SIP reuses MIME type descriptions just like email clients, so applications related to sessions can be started automatically. SIP reuses several existing relatively mature Internet services and protocols, such as DNS, RTP, RSVP, etc.


SIP is more flexible, extensible, and open. It inspired the Internet and fixed and mobile IP networks to launch a new generation of services. SIP can complete network messages on multiple PCs and phones, simulating the Internet to establish a session.


SIP uses mature assembly and interconnection technology to integrate various integrated circuits such as CMOS circuits, GaAs circuits, SiGe circuits or optoelectronic devices, MEMS devices, and various passive components such as capacitors and inductors into a package to achieve integration. The function of the machine system. The main advantages include: ①Using existing commercial components and lower manufacturing costs; ②The product enters the market with a short period; ③No matter the design and process, there is greater flexibility; ④Integrating different types of circuits and components , Relatively easy to implement. The single-level integrated module (Single Integrated Module) developed by the Georgia Institute of Technology PRC (Single Integrated Module) for short is a typical representative of SIP. After the completion of the project, the packaging efficiency, performance and reliability will be increased by 10 times, and the size and cost will be greatly reduced. The goals expected to be achieved by 2010 include wiring density to 6000cm/cm2; thermal density to 100W/cm2; component density to 5000/cm2; I/O density to 3000/cm2.


Although SIP is still a new technology and is not yet mature, it is still a promising technology. Especially in China, it may be a shortcut for the development of complete systems.


  4 Thoughts and suggestions


In the face of the world's booming microelectronic packaging situation and analyzing my country's current status quo, we must think deeply about some issues.


One, attaches great importance to the vertical integration of microelectronics three-level packaging. We should take the electronic system as the leader, and influence the first, second and third level packaging, so that we can occupy the market, improve economic efficiency, and continue to develop. We once proposed to use mobile phones and radars as technology platforms to develop our country's microelectronics packaging because of this consideration.


Two, attach great importance to the intersection and integration of different fields and technologies. The intersection and fusion of different materials produce new materials; the intersection and fusion of different technologies produce new technologies; the intersection and fusion of different fields produce new fields. In the past, there were a lot of exchanges in the same industry, but not enough exchanges in different industries. We should give full play to the role of each branch of the Institute of Electronics, and actively organize such technical exchanges.


Three. Microelectronics packaging and electronic products are inseparable. It has become the core technology that restricts the development of electronic products and even systems. It is one of the advanced manufacturing technologies in the electronics industry. Whoever masters it will master the future of electronic products and systems.


Four, microelectronics packaging must advance with the times to develop. The history of international microelectronic packaging proves this point. How does my country's microelectronic packaging advance with the times? The most urgent task is to study the development strategy of my country's microelectronic packaging and formulate a development plan. The second is to optimize the scientific research and production system of my country's microelectronic packaging. The third is to actively advocate and vigorously develop original technologies that belong to my country's independent intellectual property rights.