PCB Tech - Parallel bus VS serial bus for high-speed PCB design

As a PCB design engineer, it is very necessary, even necessary, to have some high-speed knowledge. As far as signals are concerned, high-speed signals are usually found in various parallel buses and serial buses. Only when you know what a bus is, can you know how fast it runs, and then you can start PCB wiring.

bus

The bus is a shared physical channel for communication between two or more devices. It is a collection of signal lines and a common connection between multiple components, which is used to transmit information between each component. According to different working modes, the bus can be divided into two types: one is a parallel bus and the other is a serial bus.

parallel bus

Multiple bits of data can be transmitted at the same time, which is like a spacious road that allows multiple cars to drive side by side, and it also has two-way and one-way points.

serial bus

Only one piece of data can be transmitted at the same time, which is like a narrow road that only allows one car to walk on. The data must be transmitted one after another, which looks like a long data string, so it is called "serial".

The best example of parallel transmission is the memory chip DDR. It has a set of data lines D0-D7, plus DQS and DQM. This set of lines is transmitted together. No matter which bit has an error, the data will not be transmitted correctly. Only retransmit. Therefore, each cable of the data cable must be of equal length, and it must be wound several times.

Serial data is different. Data is transmitted one by one, and there is no connection between bits. There is no error in this bit and the next bit cannot be transmitted. Parallel data is a set of data where one bit is wrong, and the entire set of data will not work.

PCB wiring requirements

Parallel bus wiring requirements:

(1) It is recommended that the bus is preferably internally wired, and the distance between the bus and other wiring should be increased as much as possible.

(2) In addition to special requirements, the single-line design impedance is guaranteed to be 50 ohms, and the differential design impedance is guaranteed to be 100 ohms.

(3) It is recommended that the same group of buses maintain the same length of wiring, and follow a certain timing relationship with the clock line, and control the wiring length with reference to the strong results of timing analysis.

(4) It is recommended to be as close as possible to the I/O power supply or GND reference plane of this group of buses to ensure the integrity of the reference plane.

(5) A bus with a rise time of less than 1ns requires a complete reference plane and must not cross the partition.

(6) It is recommended that the lower address bus refer to the clock wiring requirements.

(7) The spacing of the serpentine winding wire shall not be less than 3 times the line width.

High-speed PCB serial bus wiring requirements

For a serial bus with a frequency higher than 100Mbps, in addition to following the general crosstalk control and wiring rules for parallel buses, some additional requirements need to be considered in the wiring design:

(1) The high-speed PCB serial bus needs to consider the loss of wiring and determine the line width and line length.

(2) It is recommended that the line width is not less than 5mil under normal circumstances, and the wiring should be as short as possible.

(3) Except for the Fanout vias, the high-speed serial bus should not be punched and changed.

(4) When the speed of plug-in pins involved in the serial bus is above 3.125Gbps, the anti-pad should be optimized to reduce the impact of non-radiation caused by discontinuous impedance.

(5) It is recommended that when changing layers of high-speed serial bus wiring, choose the wiring layer with the smallest via stub. For the signal to the connector, when the wiring space is limited, the wiring layer with the short via stub is preferentially allocated to the sending end.

(6) It is recommended that when the rate is 3.125Gbps or above, a ground hole should be drilled next to the signal via, and the AC coupling capacitor should also be specially treated for the anti-pad.

(7) If the high-speed signal vias are processed by back drilling, it is necessary to consider the influence of the reduction of the current flow capacity of the power ground plane and the increase of the filter loop inductance after the flow bottleneck is narrowed.

(8) The high-speed signal avoids the dividing line of the plane layer, and the horizontal distance between the edge of the signal line and the edge of the dividing line is guaranteed to be 3W.

(9) High-speed signals in both directions should not be crossed and routed.