PCB Tech - PCB design method of DDR high-speed signal

With the rapid development of the semiconductor industry, more and more high-speed, high-function, high-precision packaged devices are applied to the system design of modern car audio, especially the use of high-speed DDR with frequencies above 200MHz in electronic navigation systems, PCB designers are required to achieve strict timing matching in order to achieve the design goals, SI and electromagnetic interference (EMI) design rules to meet the signal integrity of the waveform. This article takes DDR200 as an example to introduce the PCB design method of high-speed DDR in the car audio electronic navigation system.

In the late 1960s, car audio with a single radio function began to be applied to cars. With the improvement of modern electronic technology, car audio is also accompanied by the development of diversified products such as single-disc CD players, multi-disc CD combinations, amplifiers, speakers, subwoofers, etc., with the support of quality, technology, functions, and sound effects. To the field of multimedia systems. Especially since the beginning of the 21st century, with the advent of the DVD era and the successful development of GPS satellite navigation software and hardware, automotive electronics design has been introduced to the development direction of intensive functions such as DVD, navigation, reversing video, and TV. Improve vehicle driving, safety,

entertainment and other functions. While the function of car audio products continues to improve, it also brings unprecedented challenges to system designers: With the increase of the device clock operating frequency, the most advanced devices can be used to design high-performance products in an efficient and fast way.

In the system design of car audio in the past, the highest clock frequency on a PCB is already very high at 30~50MHz, but now the clock frequency of most PCBs exceeds 100MHz, and some even reach the order of GHz. For this reason, the traditional serial design method driven by the netlist can no longer meet today's design requirements. Now it is necessary to adopt an updated design concept and design method. Design a parallel process in which all links are considered in parallel. That is to say, the design requirements and constraints that were only considered in the PCB layout and wiring stages in the past are changed to give sufficient attention and evaluation in the schematic design stage, and the selection of key components will be analyzed at the early stage of the design, and the design of key network lines will be conceived. Topological structure, termination and matching network settings, and fully consider the PCB stack structure before the start of wiring, reduce crosstalk between signals, and ensure power integrity and timing factors.

This article mainly introduces the high-speed DDR200 used in the car audio navigation system. Under the guidance of the basic theory and professional design experience of high-speed circuits, PCB design methods to ensure signal integrity.

What is DDR and its basic working principle

DDR SDRAM, habitually called DDR. DDR SDRAM is double-rate synchronous dynamic random access memory.

DDR memory is developed on the basis of SDRAM memory. SDRAM transmits data only once in a clock cycle, it transmits data in the rising period of the clock; while DDR memory transmits data twice in a clock cycle, it can transmit data once in the rising period and the falling period of the clock., So it is called double-rate synchronous dynamic random access memory. DDR memory can achieve double data transfer rate at the same bus frequency as SDRAM.

CLK# is opposite to the normal CLK clock phase and forms a differential clock signal. The data transmission is carried out at the intersection of CLK and CLK#, that is, data is triggered on both the rising and falling edges of CLK (this happens to be the rising edge of CLK#), thereby realizing double-rate transmission.

DQS (DQ Strobe, data selection pulse) is an important function in DDRSDRAM, which is mainly used to accurately distinguish each transmission cycle within a clock cycle, and use DQS at the receiving end to read the corresponding data DQ.

DQS is valid on both rising and falling edges, and is generated at the same time as the data signal. DQS and DQ are both tri-state signals for bidirectional transmission. During a read operation, the edge of the DQS signal is aligned with the edge of the DQ signal in timing, and during a write operation, the edge of the DQS signal is aligned with the center of the DQ signal in timing.

Take the DDR SDRAM read operation timing diagram as an example to illustrate the control principle of DQS:

1. When there is no data output, DQS is at a high impedance level.

2. After receiving the READ command, the DQS signal becomes low impedance and one cycle ahead of the data output time.

3. The D Q S signal is generated at the intersection of CLK and CLK# at the same time as the data signal, and the frequency is the same as that of CLK.

4. The DQS signal continues until the read pulse burst is over, and then returns to the high impedance level again after it is over.

2 Basic specifications

The basic specifications of DDR SDRAM.

3 PCB design method of DDR200