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PCB Tech

Explanation of test technology based on high-speed PCB interconnection design
2021-08-16
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Author:ipcb

PCB interconnection design technology includes testing, simulation and various related standards, among which testing is a method and means to verify the results of various simulation analysis. Excellent test methods and methods are necessary to ensure the design and analysis of PCB interconnection. For traditional signal waveform testing, the main concern is the length of the probe lead to avoid Pigtail from introducing unnecessary noise. This article mainly discusses the new application and development of interconnection test technology.


In recent years, as the signal rate continues to increase, the test object has changed significantly. It is no longer limited to the traditional oscilloscope test signal waveform. Power ground noise, synchronous switching noise (SSN), and jitter (Jitter) have gradually become The focus of PCB interconnection design engineers, some instruments in the RF field have been applied to PCB interconnection design. Commonly used test instruments in PCB interconnection design include spectrum analyzers, network analyzers, oscilloscopes, and various probes and fixtures used by these instruments. In order to adapt to the ever-increasing signal rate, the use of these test instruments has undergone significant changes . This article uses these test instruments as tools, and mainly introduces the development of PCB interconnection design and test technology in recent years from the following aspects.


1. Calibration method for testing

2. Modeling method of passive components

3. Power integrity test

4. Clock signal jitter test method


At the end of the article, a brief introduction to the development of future test technology will be given in conjunction with the just-concluded DesignCon2005 conference.


  Calibration method


Among the three commonly used test instruments, the calibration method of the network analyzer is the most rigorous, followed by the spectrum analyzer, and the calibration method of the oscilloscope is the simplest. Therefore, we mainly discuss the calibration method of the network analyzer here. There are three commonly used calibration methods for network analyzers, Thru, TRL and SOLT.


   There are three methods, Thru, TRL and SOLT


The essence of Thru is normalization. During calibration, the network analyzer records the test result of the fixture (S21_C). In the actual test, the test result (S21_M) is directly divided by S21_C to obtain the test result of the DUT (S21_A) . Thru calibration ignores the reflection caused by the mismatch in the test fixture and the electromagnetic coupling in the space, so it has the lowest calibration accuracy. This calibration method can be used when only S21 is tested and the test accuracy is not high.


In non-Coaxial structures such as PCBs, it is sometimes necessary to test the characteristics of traces, vias, and connectors. In this case, the test instrument supplier does not provide standard calibration parts, and it is difficult for testers to make good calibration parts such as open circuit, short circuit, and matched load at the test calibration port. Therefore, traditional SOLT calibration cannot be done. The advantage of using TRL calibration is that no standard calibration parts are needed, and the test calibration port can be extended to the required position. At present, TRL calibration has been widely used in PCB structure testing.


SOLT is generally regarded as a standard calibration method. There are 12 calibration error parameters in the calibration model. Various errors are calibrated by using short circuit, open circuit, load, and through-pass. Since test equipment suppliers usually only provide Coaxial calibration parts, SOLT calibration methods cannot be used in non-Coaxial structures.


The above three calibration methods can all be analyzed in detail by means of signal flow diagrams, in which each error parameter has a corresponding parameter in the signal flow diagram. Through the signal flow diagram, you can clearly understand the error sensitivity of various calibration methods, and thus understand the error range of the actual test. The point that needs to be raised here is that even with the standard SOLT calibration method, five error parameters are ignored in the calibration model. Under normal circumstances, these five error parameters will not affect the calibration accuracy. However, if you do not pay attention to the design of the calibration fixture during use, it will be impossible to calibrate.


The spectrum analyzer provides a standard source for calibration. When calibrating, you only need to connect the internal standard source to the input port through the test fixture. The calibration time is about 10 minutes. The calibration of the oscilloscope is even simpler. Connect the probe to the internal standard source and confirm. The calibration takes about 1 minute.


   Passive component testing and modeling


With the continuous increase of signal rates, the role of passive devices in the signal link becomes more and more important. The accuracy of system performance simulation analysis is often determined by the accuracy of the passive device's model. Therefore, the testing and modeling of passive components has gradually become an important part of the PCB interconnection design of various equipment suppliers. Commonly used passive components are as follows:


1. Connector

2. PCB traces and vias

3. capacitance

4. Inductance (magnetic beads)


In the high-speed signal integrity design, the connector has the greatest impact on the signal link. For frequently used high-speed connectors, the usual practice is to make a calibration fixture according to the TRL calibration method, and perform test modeling on the connector for simulation analysis. The test modeling method of PCB traces and vias is similar to that of connectors. TRL calibration is also used to move the test port to the desired position, and then test modeling.


The capacitance model has applications in signal integrity analysis, and more importantly, it is used in power integrity analysis. The commonly used capacitance modeling instruments in the industry are impedance analyzers and network analyzers, which are suitable for different frequency bands. Impedance analyzers are suitable for low frequency bands, and network analyzers are suitable for high frequency bands. If a network analyzer is used for power integrity testing in the actual test, it is recommended to use the network analyzer in the full frequency band of the capacitance modeling to ensure the consistency of modeling and application. Because the impedance of the capacitor is small, the parallel mode is usually used when modeling with a network analyzer. At present, the unsolved problem in capacitor modeling in the industry is how to eliminate the mutual coupling between the fixture and the capacitor, so as to reduce the influence of the fixture on the modeling result.


In traditional power supply design, inductors (magnetic beads) are often used to isolate the power supply to reduce noise interference. In actual design, the isolation inductance (magnetic beads) is often removed, and the noise of the power supply is reduced. This is because the inductor (magnetic beads) resonates with other filter components. In order to avoid this situation, it is necessary to model and simulate the inductance (magnetic beads) to avoid resonance. The commonly used inductance (magnetic bead) modeling method in the industry also uses a network analyzer. The specific method is similar to capacitance modeling. The difference is that the inductor (magnetic bead) is modeled in series and the capacitor is modeled in parallel.


The modeling of the above several passive components is mainly used in signal integrity and power integrity. In recent years, EMI simulation analysis is gradually developing, and the test modeling of EMI passive components has gradually become the design of PCB interconnection. Focus. Figure 1 shows the impedance curve of the capacitor.

ATL

   power integrity test


As chip power continues to increase and operating voltage continues to decrease, power supply noise has gradually become an object of concern in PCB interconnection design. From the perspective of the test object, the power integrity test can be divided into two steps, the power system characteristic test and the power ground noise test. The former is to test the performance of the power supply part of the system (passive test), and the latter is to directly test the power ground noise when the system is working (active test). Synchronous switching noise can also be classified as power ground noise.


When testing the performance of the power system, a network analyzer is usually used, and the test objects are the Self-Impedance and Transfer-Impedance of the power system. In general, the impedance of the power system is much smaller than the impedance of the network analyzer system (50 ohms), so you only need to do through calibration during the test. The impedance of the power system can be obtained by using the formula S21=Z/25. Figure 2 shows the power supply impedance characteristics of a single board.


You can use a spectrum analyzer and an oscilloscope to test the noise of the power supply. The input port of the spectrum analyzer cannot be connected to the DC component. Therefore, when testing the noise of the power supply, you must connect DC-Blocking in series in the test fixture. The input impedance of the spectrum analyzer is 50 ohms, and the impedance of the power ground network is generally in the milliohm level, so the test fixture will not affect the system under test. The input impedance of the oscilloscope changes with different settings. Take Tektronix TDS784 as an example, its low-frequency cut-off frequency changes with the coupling mode and system impedance.


The methods described above all test the power ground noise on the single board, and what really affects the work of the chip is the power ground noise in the chip. At this time, it is necessary to use the synchronous switching noise test to determine the power ground noise in the chip. Suppose the chip has N IO ports, make one of them remain static, and the other N-1 are flipped at the same time, to test the signal waveform on the static network, that is, the synchronous switching noise. Synchronous switching noise includes both power and ground noise and crosstalk between different signals in the package. There is currently no way to completely distinguish the two.


   Clock signal jitter test


In some high-end products, jitter has gradually become an important indicator that affects product performance. Here is only a brief introduction on how to use a spectrum analyzer to test clock signal jitter and problem location. The jitter test of data signals is not involved for the time being.


In most systems, the clock is generated by a crystal oscillator or a phase-locked loop. The jitter test of the clock signal is relatively simple, no high-end test equipment is required, and a common spectrum analyzer can be used to locate the problem. The spectrum of an ideal clock signal is a clean discrete spectrum, with only components at multiples of the clock frequency. If the clock signal jitters, side lobes will appear near these multipliers, and the jitter is proportional to the power of these side lobes.


The specific method of using a spectrum analyzer to test the clock jitter is to find a testable point on the clock signal link, connect the signal to the spectrum analyzer through DC-Blocking, and observe the test result. Since the test fixture is a linear system, there is no need to worry about generating new spectral components. As mentioned earlier, clocks are all generated by crystal oscillators or phase-locked loops. In this case, the important reason for introducing clock jitter is the power supply noise of the crystal oscillators or phase-locked loops. The power supply noise of the crystal oscillator or phase-locked loop obtained by the method described above is compared with the side lobe in the clock spectrum, and the cause of the clock jitter can be basically determined. The solution to the problem is to redesign the filter circuit of the crystal oscillator or the phase-locked loop according to the side lobe of the clock spectrum. In general, these problems can be solved by a reasonable selection of filter capacitors.


  Technical direction of DesignCon2005


DesignCon is the first conference in the field of interconnection technology every year. In this year's DesignCon2005, there are mainly the following technological development trends at the annual conference:


1. There are already many applications in the industry for pure power integrity simulation and testing, and it is no longer a difficult point in the analysis work.


2. The modeling of capacitance and inductance (magnetic beads) has been promoted in the industry, and its method has been relatively complete.


3. The focus of PCB interconnection design has shifted to packaging, and board-level analysis has become more mature. Simultaneous switching noise simulation and testing have gradually become a concern in the industry.


4. Jitter test methods and standards have gradually become a concern of the industry. At the conference, many test equipment suppliers launched their own jitter analyzers.


  Summarize 


This article briefly introduces the current test objects and test methods in the field of PCB interconnection design. As the signal rate continues to increase, some new test content gradually appears, including power supply and ground noise, passive device modeling, jitter, and so on. The author proposes a test method for these new test contents based on his own work experience. In the traditional signal waveform test, the main consideration should be to reduce the length of the ground wire to avoid Pigtail coupling into noise and reduce the test accuracy. In the future PCB interconnection design, due to the increase in signal operating frequency, the focus of work will shift to chip packaging, and related testing and modeling techniques will become the focus of work.