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PCB layout design review elements
PCB News
PCB layout design review elements

PCB layout design review elements


DFM requirements for layout


1 The optimal process route has been determined, and all devices have been placed on the board.

2 The origin of the coordinates is the intersection of the left and bottom extension lines of the board frame, or the bottom left pad of the bottom left socket.

3 The actual size of the PCB board, the location of the positioning components, etc. are consistent with the process structure element map, and the device layout of the area with restricted device height requirements meets the requirements of the structure element map.

4 The position of the DIP switch, reset device, indicator light, etc. is appropriate, and the handle bar does not interfere with the surrounding devices.

5 The outer frame of the board has a smooth radian of 197mil, or is designed according to the structure size drawing.

6 The ordinary board has 200mil process edges; the left and right sides of the backplane have process edges greater than 400mil, and the upper and lower sides have process edges greater than 680mil. The device placement does not conflict with the window opening position.

7 All kinds of additional holes (ICT positioning hole 125mil, handle bar hole, elliptical hole and fiber holder hole) that need to be added are all omitted and set correctly.

8 The device pin pitch, device direction, device pitch, device library, etc. that have been processed by wave soldering take into account the requirements of wave soldering.

9 The device layout spacing meets the assembly requirements: surface mount devices are greater than 20mil, IC is greater than 80mil, and BGA is greater than 200mil.

10 The crimping part has a component with a distance higher than that of the device greater than 120mil, and there is no device in the through area of the crimping part on the welding surface.

11 There are no short or short devices between high devices, and no patch devices and short and small interposing devices are placed within 5mm between devices with a height greater than 10mm.

12 Polar devices are marked with polarity silkscreen. The X and Y directions of the same type of polarized plug-in components are the same.

13 All devices are clearly marked, no P*, REF, etc. are not clearly marked.

14 There are 3 positioning cursors on the surface containing SMD devices, which are placed in an "L" shape. The distance between the center of the positioning cursor and the edge of the board is greater than 240 mils.

15 If you need to do boarding processing, the layout is considered to be easy to make up, and it is convenient for PCB processing and assembly.

16 The chipped edges (abnormal edges) should be filled in by means of milling grooves and stamp holes. The stamp hole is a non-metallized void, generally 40 mils in diameter and 16 mils from the edge.

17 The test points used for debugging have been added in the schematic diagram, and they are placed appropriately in the layout.

Thermal design requirements for layout
18 Heating components and exposed components of the enclosure should not be in close proximity to wires and heat-sensitive components, and other components should also be kept away from them.

19 The placement of the radiator takes into account the problem of convection, and there is no interference of high components in the projection area of the radiator, and the range is marked on the mounting surface with silk screen.

20 The layout takes into account the reasonable and smooth heat dissipation channels.

21 The electrolytic capacitor should be properly separated from the high-heat device.

22 Consider the heat dissipation of high-power components and components under the subboard.

Signal integrity requirements for layout
23 The start end match is close to the originating device, and the end match close to the receiving end device.

24 Decoupling capacitors are placed close to related devices

25 Crystals, crystal oscillators and clock drive chips are placed close to related devices.

26 High-speed and low-speed, digital and analog are arranged separately according to modules.

27 Determine the topological structure of the bus based on the analysis and simulation results or the existing experience to ensure that the system requirements are met.

28 If it is to modify the board design, simulate the signal integrity problem reflected in the test report and give a solution.

29 The layout of the synchronous clock bus system meets the timing requirements.

EMC requirements
30 Inductive devices that are prone to magnetic field coupling, such as inductors, relays, and transformers, should not be placed close to each other. When there are multiple inductance coils, the direction is vertical and they are not coupled.

31 In order to avoid electromagnetic interference between the devices on the welding surface of the single board and the adjacent single board, no sensitive devices and strong radiation devices are placed on the welding surface of the single board.

32 The interface components are placed close to the edge of the board, and appropriate EMC protection measures have been taken (such as shielding shells, hollowing out of the power supply ground, etc.) to improve the EMC capability of the design.

33 The protection circuit is placed near the interface circuit, following the principle of first protection and then filtering.

34 The distance from the shielding body and the shielding shell to the shielding body and shielding cover shell is more than 500 mils for the devices with high transmitting power or particularly sensitive (such as crystal oscillators, crystals, etc.).

35 A 0.1uF capacitor is placed near the reset line of the reset switch to keep the reset device and reset signal away from other strong interference components and signals.

Layer setting and power ground splitting requirements
37 When two signal layers are directly adjacent to each other, vertical wiring rules must be defined.

38 The main power layer is adjacent to its corresponding ground layer as much as possible, and the power layer meets the 20H rule.

39 Each wiring layer has a complete reference plane.

40 Multi-layer boards are laminated and the core material (CORE) is symmetrical to prevent the uneven distribution of the copper skin density and the asymmetrical thickness of the medium from warping.

41 The thickness of the board should not exceed 4.5mm. For those with a thickness greater than 2.5mm (backplane greater than 3mm), the technicians should have confirmed that there is no problem with the PCB processing, assembly and equipment, and the PC card board thickness is 1.6mm.

42 When the thickness-to-diameter ratio of the via is greater than 10:1, it will be confirmed by the PCB manufacturer.

43 Separate the power and ground of the optical module from other power and ground to reduce interference.

44 The power and ground processing of key components meet the requirements.

45 When impedance control is required, the layer setting parameters meet the requirements.

Power module requirements
46 The layout of the power supply section ensures that the input and output lines are smooth and do not cross.

47 When the single board supplies power to the subboard, place the corresponding filter circuit near the power outlet of the single board and the power inlet of the subboard.

Other requirements
48 The layout takes into account the smoothness of the overall wiring, and the main data flow is reasonable.

49 According to the layout results, adjust the pin assignments of exclusion, FPGA, EPLD, bus driver and other devices to optimize the layout.

50 The layout takes into account the appropriate increase of the space at the dense wiring to avoid the situation where it cannot be routed.

51 If special materials, special devices (such as 0.5mmBGA, etc.), and special processes are adopted, the delivery period and processability have been fully considered, and confirmed by PCB manufacturers and process personnel.

52 The pin corresponding relationship of the sub-board connector has been confirmed to prevent the direction and orientation of the sub-board connector from being reversed.

53 If there are ICT test requirements, consider the feasibility of adding ICT test points during layout to avoid difficulty in adding test points during the wiring phase.

54 When a high-speed optical module is included, the layout of the optical port transceiver circuit is prioritized.

55 After the layout is completed, a 1:1 assembly drawing has been provided for the project personnel to check whether the device package selection is correct against the device entity.

56 In the window opening, the inner plane has been considered to be retracted, and a suitable wiring prohibition area has been set.

The above is an introduction to the inspection elements of PCB layout design. Ipcb is also provided to PCB manufacturers and PCB manufacturing technology.