PCB News - Board layout of high resolution ADC

High-speed ADC (Analog/Digital Converter) is a key analog processing component in various application fields (such as mass spectrometer, ultrasound, lidar/radar, telecommunication transceiver module, etc.). Whether the application is based on the time domain or the frequency domain, the highest dynamic performance of the ADC is required. Faster and higher-resolution ADCs enable the ultrasound system to have more detailed images and enable the communication system to have higher data processing capabilities.

As the sampling rate of 14-bit or higher resolution ADCs continues to increase to the 100M sampling range, system designers must become experts in clock design and distribution and board layout.
This article describes some key issues in system design, with particular attention to printed circuit board (PCB) ground and power plane wiring technology. A modern ADC requires a modern board design. Without an accurate clock source or carefully designed board layout, the high-performance converter will not reach its performance indicators.
Single IF heterodyne receiver structure and advanced power amplifier linearization algorithm are putting forward requirements on ADC performance. Such a system is pushing the inherent jitter performance of the converter to below 1/2 PS. Similarly, test instrument engineers need to have very low noise performance in broadband for the development of advanced spectrum analyzers.
Therefore, the most important sub-circuit in the high-speed data conversion system is the clock source. This is because the timing accuracy of the clock signal will directly affect the dynamic performance of the ADC.
To minimize this effect, the ADC clock source must have very low timing jitter or phase noise. If this factor is not considered when selecting the clock circuit, the dynamic performance of the system will not be good. This has nothing to do with the quality of the front-end analog input circuit or the inherent jitter performance of the converter. A precise clock can always provide edge transitions at precise time intervals.
In fact, clock edges arrive at continuously changing time intervals. Therefore, the uncertainty of this timing can be used to comprehensively evaluate the signal-to-noise ratio of the sampled waveform by means of the data transformation process.
The maximum clock jitter is determined by the following formula:
Tj(rms)=(VIN(p-p) /VINFSR)*(1/(2(N+1)*π*fin)
If the input voltage (VIN) is equal to the full scale range of the ADC (VINFSR), the jitter requirement becomes a factor of the ADC resolution (N bits) and the sampled input frequency (fin).
For a 70MHz input frequency, the total jitter requirement is:
Tj(rms)=1* (1/215π*70*106))
Tj(rms)=140fs
Since many systems distribute the reference clock through the backplane or another connection, which will reduce the signal quality, the local oscillator (VCXD with low phase noise) is usually used as the timing source of the ADC. Figure 1 shows the use of NS's LMX2531 clock synthesis to achieve timing generation. The LMX2531 connected to the timing generator is output by the programmable frequency divider synthesizer, giving a jitter performance of less than 100 femtoseconds.

The above is an introduction to the PCB board layout of high-resolution ADCs. Ipcb is also provided to PCB manufacturers and PCB manufacturing technology.