PCB Tech - What to pay attention to in the PCB design process

1. Design output

The PCB design can be exported to a printer or a gerber file. The printer can print the PCB layers, which is convenient for the designer and reviewer to check; the gerber file is handed over to the board manufacturer to produce the printed board. The output of the gerber file is very important. It is related to the success or failure of this design. The following will focus on the matters needing attention when outputting the gerber file.

a. The layers that need to be output are wiring layer (including top layer, bottom layer, middle wiring layer), power layer (including VCC layer and GND layer), silk screen layer (including top silk screen, bottom silk screen), solder mask (including top solder mask) And bottom solder mask), and also generate a drilling file (NC Drill) b. If the power layer is set to Split/Mixed, then select Routing in the Document item of the Add Document window, and each time the gerber file is output, you must Use Pour Manager's Plane Connect to pour copper on the PCB diagram; if it is set to CAM Plane, select Plane. When setting the Layer item, add Layer25, and select Pads and Viasc in the Layer25 layer. In the device settings window ( Press Device Setup) and change the value of Aperture to 199d. When setting the Layer of each layer, select the Board Outline. e. When setting the Layer of the silk-screen layer, do not select Part Type, select the top layer (bottom layer) and the Outline of the silk-screen layer, Text, Linef. When setting the layer of the solder mask layer, select vias to indicate that no solder mask is added to the vias, and not to select vias to indicate solder masks, which are determined according to the specific situation. g. When generating a drilling file, use PowerPCB defects Save settings, do not make any changes. h. After all the gerber files are output, open and print them with CAM350, and the designers and reviewers will check the vias (via) according to the "PCB checklist", which is one of the important components of the multilayer PCB. The cost of drilling usually accounts for 30 to 40 of the cost of PCB manufacturing. Simply put, every hole on the PCB can be called a via. From the point of view of function, vias can be divided into two categories:

2. It is used as an electrical connection between each layer;

It is used to fix or locate the device. In terms of process, these vias are generally divided into three categories, namely blind vias, buried vias and through vias. Blind holes are located on the top and bottom surfaces of the printed circuit board and have a certain depth. They are used to connect the surface line and the underlying inner line. The depth of the hole usually does not exceed a certain ratio (aperture). Buried hole refers to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board. The above-mentioned two types of holes are located in the inner layer of the circuit board, and are completed by a through-hole forming process before lamination, and several inner layers may be overlapped during the formation of the via.

The third type is called a through hole, which penetrates the entire circuit board and can be used for internal interconnection or as a component mounting positioning hole. Because the through hole is easier to implement in the process and the cost is lower, most of the printed circuit boards use it instead of the other two types of through holes. The following via holes, unless otherwise specified, are considered as via holes. From a design point of view, a via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole, as shown in the figure below. The size of these two parts determines the size of the via.

Obviously, in high-speed, high-density PCB design, designers always hope that the smaller the via hole is, the better, so that more wiring space can be left on the board. In addition, the smaller the via hole, the parasitic capacitance of its own. The smaller it is, the more suitable it is for high-speed circuits. However, the reduction of hole size also brings about an increase in cost, and the size of vias cannot be reduced indefinitely. It is restricted by process technologies such as drilling and plating: the smaller the hole, the drill The longer the hole takes, the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, it cannot be guaranteed that the hole wall can be uniformly plated with copper. For example, the thickness (through hole depth) of a normal 6-layer PCB board is about 50Mil, so the minimum drilling diameter that PCB manufacturers can provide can only reach 8Mil.

3. Parasitic capacitance of vias

The via itself has a parasitic capacitance to the ground. If it is known that the diameter of the isolation hole on the ground layer of the via is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, the size of the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1) The parasitic capacitance of the via will cause the circuit to prolong the rise time of the signal and reduce the speed of the circuit. For example, for a PCB with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used.

The distance between the pad and the ground copper area is 32Mil, then we can approximate the parasitic capacitance of the via through the above formula is roughly: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF, this part The change in rise time caused by the capacitance is: T10-90=2.2C(Z0/2)=2.2x0.517x(55/2)=31.28ps. It can be seen from these values that although the effect of the rise delay caused by the parasitic capacitance of a single via is not obvious, if the via is used multiple times in the trace to switch between layers, the designer should still consider carefully.

4. Parasitic inductance of vias

Similarly, there are parasitic capacitances along with vias. In the design of high-speed digital circuits, the damage caused by the parasitic inductance of the vias is often greater than the impact of the parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can use the following formula to simply calculate the approximate parasitic inductance of a via = 5.08h [ln(4h/d) 1] where L refers to the inductance of the via, h is the length of the via, and d is the center drilled hole diameter. It can be seen from the formula that the diameter of the via has a small influence on the inductance, and the length of the via has the greatest influence on the inductance. Still using the above example, the inductance of the via can be calculated as =5.08x0.050 [ln(4x0.050/0.010) 1]=1