PCB Tech - PCB design methods and skills 2

21. Which aspects should the PCB board DEBUG start from?
As far as digital circuits are concerned, first determine three things in order:

1. Confirm that all power supply values meet the design requirements. Some systems with multiple power supplies may require certain specifications for the order and speed of the power supplies.
2. Confirm that all clock signal frequencies are working properly and there are no non-monotonic problems on the signal edges.
3. Confirm whether the reset signal meets the specification requirements.
If these are normal, the chip should send out the first cycle (cycle) signal. Next, debug according to the operating principle of the system and the bus protocol.
22. When the size of the circuit board is fixed, if the design needs to accommodate more functions, it is often necessary to increase the trace density of the PCB, but this may increase the mutual interference of the traces, and at the same time, the impedance of the traces is too thin Can't be reduced, please introduce the skills in high-speed (>100MHz) high-density PCB design?
When designing high-speed and high-density PCBs, crosstalk interference (crosstalk interference) really needs special attention, because it has a great impact on timing and signal integrity. Here are a few points to note:
1. Control the continuity and matching of the characteristic impedance of the wiring.
2. The size of the trace spacing. The commonly seen spacing is twice the line width. It is possible to know the influence of trace spacing on timing and signal integrity through simulation, and find the minimum tolerable spacing. The result of different chip signals may be different.
3. Choose the appropriate termination method.
4. Avoid two adjacent layers with the same wiring direction, even if the wiring overlaps up and down, because this kind of crosstalk is larger than that of adjacent wiring on the same layer.
5. Use blind/buried vias to increase the trace area. However, the manufacturing cost of the PCB board will increase.
It is indeed difficult to achieve complete parallelism and equal length in actual implementation, but it is still necessary to do it as much as possible. In addition, differential termination and common mode termination can be reserved to alleviate the impact on timing and signal integrity.
23. The filtering at the analog power supply often uses an LC circuit. But why sometimes LC is less effective than RC filtering?
The comparison of LC and RC filtering effects must consider whether the selection of the frequency band to be filtered and the inductance value is appropriate. Because the inductance (reactance) of the inductor is related to the inductance value and frequency. If the noise frequency of the power supply is low and the inductance value is not large enough, the filtering effect may not be as good as RC. However, the price to pay for using RC filtering is that the resistor itself consumes energy and has poor efficiency, and pay attention to the power that the selected resistor can withstand.
24. What is the method of selecting inductor and capacitor value for filtering?
In addition to the noise frequency that you want to filter out, the choice of inductance value should also consider the response capability of the instantaneous current. If the output terminal of the LC has a chance to output a large current instantaneously, too large an inductance value will hinder the speed of the large current flowing through the inductor and increase ripple noise.
The capacitance value is related to the size of the ripple noise specification value that can be tolerated. The smaller the ripple noise value requirement, the larger the capacitance value. The ESR/ESL of the capacitor will also have an impact.
In addition, if the LC is placed on the output terminal of a switching regulation power (switching regulation power), pay attention to the influence of the pole/zero generated by the LC on the stability of the negative feedback control loop. .
25. How to meet EMC requirements as much as possible without causing too much cost pressure?
The cost increase on the PCB due to EMC is usually due to the increase in the number of ground layers to enhance the shielding effect and the addition of ferrite bead, choke and other high-frequency harmonic suppression devices. In addition, it is usually necessary to match the shielding structure on other institutions to make the entire system pass the EMC requirements. The following only provides several PCB design techniques to reduce the electromagnetic radiation effect generated by the circuit.
1. Try to choose devices with slower signal slew rate to reduce the high frequency components generated by the signal. 2. Pay attention to the placement of high-frequency components, not too close to the external connector.
3. Pay attention to the impedance matching of high-speed signals, the wiring layer and its return current path to reduce high-frequency reflection and radiation.
4. Place sufficient and appropriate decoupling capacitors on the power supply pins of each device to alleviate the noise on the power plane and ground plane. Pay special attention to whether the frequency response and temperature characteristics of the capacitor meet the design requirements.
5. The ground near the external connector can be properly separated from the ground, and the ground of the connector can be connected to the chassis ground nearby.
6. Ground guard/shunt traces can be appropriately used beside some special high-speed signals. But pay attention to the influence of guard/shunt traces on the characteristic impedance of the trace.
7. The power layer shrinks 20H from the ground layer, and H is the distance between the power layer and the ground layer.
26. When there are multiple digital/analog function blocks in a PCB board, the conventional method is to separate the digital/analog ground. What is the reason?
The reason for separating the digital/analog ground is because the digital circuit will generate noise in the power and ground when switching between high and low potentials. The magnitude of the noise is related to the speed of the signal and the magnitude of the current. If the ground plane is not divided and the noise generated by the digital area circuit is large and the analog area circuit is very close, even if the digital-to-analog signals are not intersecting*, the analog signal will still be interfered by the ground noise. That is to say, the non-divided digital-to-analog method can only be used when the analog circuit area is far from the digital circuit area that generates large noise.
27. Another approach is to ensure that the digital/analog layout is separated, and the digital/analog signal lines do not cross each other*, the entire PCB board ground is not divided, and the digital/analog ground is connected to this ground plane. What's the reason?
The requirement that the digital-analog signal traces cannot cross* is because the return current path of the digital signal with a faster speed will flow back to the source of the digital signal along the ground near the bottom of the trace as much as possible. Line crossing*, the noise generated by the return current will appear in the analog circuit area.
28. How to consider impedance matching when designing high-speed PCB design schematics?
When designing high-speed PCB circuits, impedance matching is one of the design elements. The impedance value has an absolute relationship with the wiring method, such as walking on the surface layer (microstrip) or inner layer (stripline/double stripline), distance from the reference layer (power layer or ground layer), wiring width, PCB material, etc. Both will affect the characteristic impedance value of the trace. That is to say, the impedance value can only be determined after wiring. Generally, the simulation software cannot take into account some discontinuous wiring conditions due to the limitation of the circuit model or the mathematical algorithm used. At this time, only some terminators (termination), such as series resistance, can be reserved on the schematic diagram. Alleviate the effect of discontinuity in trace impedance. The real solution to the problem is to try to avoid impedance discontinuities when wiring.
29. Where can I provide a more accurate IBIS model library?
The accuracy of the IBIS model directly affects the simulation results. Basically, IBIS can be regarded as the electrical characteristic data of the equivalent circuit of the actual chip I/O buffer, which can generally be obtained by conversion of the SPICE model (measurement can also be used, but there are more restrictions), and the SPICE data and chip manufacturing are absolutely absolute Therefore, the SPICE data of the same device provided by different chip manufacturers is different, and the data in the converted IBIS model will also vary accordingly. In other words, if manufacturers A’s devices are used, only they have the ability to provide accurate model data for their devices, because no one else knows better than them what process their devices are made of. If the IBIS provided by the manufacturer is inaccurate, the fundamental solution can only be to continuously ask the manufacturer to improve.
30. In high-speed PCB design, which aspects should designers consider EMC and EMI rules?
Generally, EMI/EMC design needs to consider both radiated and conducted aspects. The former belongs to the higher frequency part (>30MHz) and the latter is the lower frequency part (<30MHz). So it cannot Only pay attention to the high frequency and ignore the low frequency part.
A good EMI/EMC design must take into account the location of the device, the arrangement of the PCB stack, the important connection method, the selection of the device, etc. at the beginning of the layout. If there is no better arrangement beforehand, it will be solved afterwards. It will double the effort and increase the cost. For example, the location of the clock generator should not be as close as possible to the external connector. High-speed signals should be routed to the inner layer as much as possible. Pay attention to the characteristic impedance matching and the continuity of the reference layer to reduce reflections. The slope of the signal pushed by the device (slew rate) is as small as possible to reduce high-frequency components. When choosing a decoupling/bypass capacitor, pay attention to whether its frequency response meets the requirements to reduce power layer noise. In addition, pay attention to the return path of high-frequency signal current to make the loop area as small as possible ( That is, the loop impedance is as small as possible to reduce radiation. The ground layer can also be divided to control the range of high-frequency noise. Finally, the chassis ground between the PCB and the case should be selected appropriately.
31. How to choose EDA tools?
In the current PCB design software, thermal analysis is not a strong point, so it is not recommended to use it. For other functions 1.3.4, you can choose PADS or Cadence. The cost performance is good.
Beginners in PLD design can use the integrated environment provided by PLD chip manufacturers, and can use single-point tools when designing more than one million gates.
32. Please recommend an EDA software suitable for high-speed signal processing and transmission.
For conventional circuit design, INNOVEDA's PADS is very good, and there is a matching simulation software, and this type of design often occupies 70% of the applications. When doing high-speed circuit design, analog and digital hybrid circuits, the solution using Cadence should be a software with relatively good performance and price. Of course, the performance of Mentor is still very good, especially its design flow management should be the best. (Wang Sheng, Technical Expert of Datang Telecom)
33. Interpretation of the meaning of each layer of the PCB board
Topoverlay ---- The name of the top device, also called top silkscreen or top component legend, such as R1 C5, IC10.
bottomoverlay-the same
multilayer-----If you design a 4-layer board, you place a free pad or via, and define it as a multilay, then its pad will automatically appear on the 4 layers. If you only define it as the top layer, then Its pad will only appear on the top layer.
34. What aspects should be paid attention to in the design, routing and layout of high-frequency PCBs above 2G?
High-frequency PCBs above 2G belong to radio frequency circuit design and are not within the scope of discussion of high-speed digital circuit design. The layout and routing of the radio frequency circuit should be considered together with the schematic, because the layout and routing will cause distribution effects. Moreover, some passive devices in the design of radio frequency circuits are realized through parameterized definitions and special-shaped copper foils. Therefore, EDA tools are required to provide parameterized devices and edit special-shaped copper foils.
Mentor's boardstation has a special RF design module that can meet these requirements. Moreover, general RF design requires specialized RF circuit analysis tools. The most famous in the industry is agilent's eesoft, which has a good interface with Mentor's tools.
35. What rules should be followed in the design of microstrip for high frequency PCB design above 2G?
The design of RF microstrip line requires 3D field analysis tools to extract the transmission line parameters. All rules should be specified in this field extraction tool.
36. For a PCB with all digital signals, there is an 80MHz clock source on the board. In addition to the use of wire mesh (grounding), in order to ensure sufficient drive capacity, what kind of circuit should be used for protection?
To ensure the driving capability of the clock, it should not be realized through protection, and the clock driving chip is generally used. The general concern about clock drive capability is due to multiple clock loads. Adopt the clock to drive the chip, change one clock signal into several, adopt the point-to-point connection. When selecting the drive chip, in addition to ensuring that it is basically matched with the load, the signal edge meets the requirements (usually the clock is an edge valid signal). When calculating the system timing, the delay of the clock in the drive chip should be counted.
37. If a separate clock signal board is used, what kind of interface is generally used to ensure that the transmission of the clock signal is less affected?
The shorter the clock signal, the smaller the transmission line effect. Using a separate clock signal board will increase the signal wiring length. And the grounding power supply of the single board is also a problem. If long-distance transmission is required, differential signals are recommended. The LVDS signal can meet the drive capability requirements, but your clock is not too fast and it is not necessary.