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Eight Misunderstandings of PCB Circuit Design
PCB News
Eight Misunderstandings of PCB Circuit Design

Eight Misunderstandings of PCB Circuit Design


Phenomenon 1: The PCB design requirements of this PCB board are not high, so use a thinner wire and automatically arrange it. Comment: Automatic wiring will inevitably take up a larger PCB area, and at the same time, it will produce many times more vias than manual wiring. In batches In a large product, besides business factors, the factors that PCB manufacturers consider for price reduction are line width and the number of vias, which respectively affect the yield of PCB and the number of drill bits consumed, which saves the cost of the supplier and also gives The price cut found a reason.


   Phenomenon 2: These bus signals are all pulled by resistors, so I feel relieved.

   Comment: There are many reasons why signals need to be pulled up and down, but not all of them need to be pulled. The pull-up and pull-down resistors pull a simple input signal, and the current is less than tens of microamperes, but when a driven signal is pulled, the current will reach the milliamp level. The current system often has 32 bits of address data each, and there may be If the 244/245 isolated bus and other signals are pulled up, a few watts of power consumption will be consumed on these resistors.

   Phenomenon 3: How to deal with these unused I/O ports of CPU and FPGA? Leave it empty first, and talk about it later.

   Comment: If the unused I/O port is left floating, it may become an input signal that repeatedly oscillates with a little interference from the outside world, and the power consumption of MOS devices basically depends on the number of flips of the gate circuit. If it is pulled up, each pin will also have a microampere current, so the best way is to set it to output (of course, no other signals with driving can be connected to the outside) Phenomenon 4: This FPGA has so much left You can't run out of doors, so let's play it out. Comment: The power consumption of FGPA is proportional to the number of flip-flops used and the number of flips, so the power consumption of the same type of FPGA at different circuits and different times may be 100 times different. Minimizing the number of flip-flops for high-speed flipping is the fundamental way to reduce FPGA power consumption.

Phenomenon 5: The power consumption of these small chips is very low, no need to consider the comments: it is difficult to determine the power consumption of the internally not complicated chip, it is mainly determined by the current on the pin, an ABT16244, power consumption without load Probably less than 1 mA, but its indicator is that each pin can drive a load of 60 mA (such as matching a resistance of tens of ohms), that is, the maximum power consumption of the full load can reach 60*16=960mA, of course it is only the power supply With such a large current, all the heat falls on the load.

   Phenomenon 6: The memory has so many control signals. My PCB board only needs to use the OE and WE signals. The chip select should be grounded, so that the data comes out much faster during the read operation.

Comment: The power consumption of most memories when the chip selection is valid (regardless of OE and WE) will be more than 100 times larger than when the chip selection is invalid. Therefore, CS should be used to control the chip as much as possible, and as long as other requirements are met. It is possible to shorten the width of the chip select pulse.

   Phenomenon 7: Why are these signals overshooting? As long as the matching is good, comments can be eliminated: Except for a few specific signals (such as 100BASE-T, CML), there is overshoot, as long as it is not very large, it does not necessarily need to be matched, even if it is matched, it is not necessary to match. Best. For example, the output impedance of TTL is less than 50 ohms, and some even 20 ohms. If such a large matching resistance is used, the current will be very large, the power consumption will be unacceptable, and the signal amplitude will be too small to be used. Besides, the output impedance of a general signal when outputting a high level and outputting a low level is not the same, and there is no way to achieve a complete match. Therefore, the matching of TTL, LVDS, 422 and other signals can be acceptable as long as the overshoot is achieved.

   Phenomenon 8: Reducing power consumption is a matter of hardware personnel, and has nothing to do with software