PCB Blog - A new PCB board testing technology

At present, with the continuous emergence of products using large-scale integrated circuits, the installation and testing of the corresponding PCB board have become more and more difficult. Although the traditional method of in-circuit test technology is still used for the testing of printed circuit boards, this method has become more and more problematic due to the miniaturization and packaging of chips. Now a new test technology-boundary scan test technology has been gradually developed, most ASIC circuits and many medium-scale equipment have begun to use the boundary scan test technology to design. BST technology is in accordance with the IEEE1149.1 standard and provides a complete set of testing solutions. In the actual test, it does not need to resort to complex and expensive test equipment, and provides a test method independent of circuit board technology. The advantages of using boundary scan test technology for integrated circuit design and printed circuit board design are that the test process is simple, which significantly reduces the test and diagnosis time in the process of production, experiment, use and maintenance, thus greatly reducing the cost.

1. The basic composition of BST
The BST circuit is constructed in accordance with the IEEE1149.1 standard, which includes the test access channel TAP and the controller, the instruction register IR and the test data register group TDR. The test access channel TAP is a 5-pin pin (1-pin is the reset terminal) connector. The TAP controller is a 16-state state machine, which can generate clock signals and various control signals (ie, generate test, shift, capture, and update signals), so that instructions or test data are shifted into the corresponding registers, and control the boundary scan Various working states of the test.

1.1 Test the clock input terminal TCK
The TCK signal allows the boundary scan portion of the integrated circuit IC to be synchronized with the clock within the system and operate independently.

1.2 Test mode selection input TMS
The test mode selects the TMS pin as the control signal, which determines the working state of the TAP controller. TMS must be established before the rising edge of TCK.

1.3 Test data input terminal TDI
On the rising edge of the test clock pulse TCK, the data serially inserted through TDI is shifted into the instruction register or the test data register, and the TAP controller determines whether the shifted data is instruction or test data.

1.4 Test data output terminal TDO
At the falling edge of the test clock pulse TCK, the data is serially output from the instruction register or the test data register through TDO, and the TAP controller determines whether the serialized data is the instruction or test data.

2. PCB board test system
2.1 Test system structure
Its hardware includes a general PC, a BST tester and a serial BST signal cable (a bus with 4 signals, the meanings of the numbers in the figure are as follows: 1 is TDI, 2 is TCK, 3 is TMS, and 4 is TDO). The tester is connected to the PC through a standard parallel port, and is connected to the test access port TAP on the PCB through a serial signal cable. Assuming that there are three modules A, B, and C on the printed circuit board, the module can be composed of a single chip or multiple chips. They are designed according to the IEEE1149.1 standard, that is, the BS register (the position where the dotted line passes in the module) is added to the I/O pin of the chip, and the boundary scan test can be performed. If the designed digital system or equipment has multiple PCB boards, it can be connected to the PCB boards through serial signal cables. Users can flexibly select chips, modules or the entire PCB to be tested through programming.

2.2 Principle of test system
Testers can use PC software programming to automatically generate test patterns to detect circuit faults according to the netlist and device model of the PCB board. The PC should have two boards with at least 32-bit I/O pins, so that 32-bit read/write pins can be formed to facilitate read and write operations. Test software should include preprocessors and execution units. The preprocessor reads out the test graphs and obtains the possible relationships of these graphs, and the result is a set of files, including storage and control information. The execution unit loads the above files and then executes the tests. The process is to read the stored information first, put the data on the input port, read the data from the appropriate output port, and compare it with the expected result. If a fault is found, a fault will be generated, and the location of the fault will be marked, and a diagnostic program will be added to give the specific location of the fault.

2.3 Test content
1) Test the connection of the I/O pins of the PCB board. Because the I/O pins of the PCB board provide access channels for the tester;
2) Test the integrity of the IC chip on the PCB board. During the assembly process of the chip, the IC chip may have been damaged. The built-in self-test and internal test can be used to verify the quality of the chip;
3) Test the open circuit and short circuit faults of the IC chip interconnection on the PCB board, which can be verified by external tests:
4) Test the integrity of the bus on the PCB board, through which the test can detect whether there is an open circuit fault on the I/O pins of the IC chip connected to the bus.
With the continuous development of BST technology, PCB board testing will be gradually improved. Due to the extensive use of programmable integrated circuits, the flexibility and applicability of PCB board testing will be improved, and the cost of the corresponding test system will be reduced. Designers can use all programmable logic integrated circuits on the PCB board, and the chip logic can be modified only by software programming, so as to make a general printed circuit board, so that the PCB board can complete different functions. In this way, the boundary scan test technology will make the PCB board test more convenient and fast, and greatly reduce the test cost.