PCB Blog - Methods of designing signal problems on high-speed PCB board

In high-speed PCB board design, the impact of signal integrity problems on the reliability of circuit design is becoming more and more obvious. In order to solve the signal integrity problems, design engineers put more time and energy into the constraint definition stage of circuit board design. By using design-oriented signal analysis tools early in the design process, running multiple simulations, and carefully planning the board topology, comprehensive design constraints for electrical and physical characteristics can be developed to avoid EMI and other related issues. The current typical design environment is mostly oriented to the later stage of design, with circuit board drawing as the main consideration. Design tool providers are now addressing these new design challenges. But design engineers need a new approach to solving the increasingly prominent high-speed design problems in design, with which design engineers can solve problems early in the design process.

Tighter tool integration
To identify and resolve these high-speed signal problems without relying on expensive and time-consuming board testing steps, it is critical to perform extensive signal analysis prior to board design. When design engineers identify these problems, they can ensure circuit design success by changing the routing and circuit layer distribution, defining the routing topology of the clock lines, and selecting components at specific speeds. However, previous signal integrity analysis tools have been very limited, either not easy to use, or do not have the ability to analyze the entire design. Therefore, design engineers can only rely on experience to determine the key circuit networks that need attention, or rely on comprehensive signal integrity analysis tools to analyze. Design tools began to break new ground, developing effective analysis tools for high-speed design problems. Take the signal integrity analysis tools provided by Innoveda as an example. The company's HyperLynx toolset is easy to use and can provide powerful signal integrity analysis functions before and after board drawing. One of its outstanding features is a very user-friendly interface, which allows design engineers to quickly analyze the "possible scenarios" they envision and experiment with problems such as terminal topologies to quickly find solutions that meet performance and reliability . For engineers dealing with high-complexity boards and systems, Innoveda's XTK Signal Integrity Verification Toolset and ePlanner Signal Integrity Planning Environment provide advanced algorithms and some proven validation for ultra-high-speed signal integrity analysis Features including topology analysis, high-speed sweeps and lossy lines, Monte Carlo methods, and algorithms for signal integrity analysis. In the past design engineers had to choose between Hyperlynx and XTK. Recently, Innoveda has implemented the connection between these two key signal integrity analysis tools, which integrates the two together, and can use both tools in one design, which can effectively shorten the design cycle. Typically, HyperLynx started out as a tool for high-speed PCB signal analysis, while XTK and ePlanner were used for more complex topology analysis and constraint generation.

Enhanced wiring capabilities
After determining the routing rules, the design engineer moves to the physical implementation of the design. Common PCB board drawing tools provide comprehensive component selection capabilities, the ability to set board layers, assign constraint rules and manage the placement of all components on the board. A good tool must be easy to use, automatically manage all design constraints, and produce the final board design. But this is not enough in a high-speed design environment, and PCB board drawing tools must provide a more comprehensive solution. At present, some designs are usually very complex and the development time is short. Design engineers can no longer use the manual drawing method of the past, otherwise it is time-consuming and error-prone. In order to maximize productivity and solve a large number of signal analysis problems, design engineers need a tool that allows them to perform routing in batch mode as well as interactively. The PowerPCB board 5.0 released by Innoveda meets this design requirement. This shape-and-rule-based board design system includes the BlazeRouter HSD (High Speed Design), a high-speed design option that allows automatic routing based on high-speed constraints including /length, matching length, and differential pair (differential paIR). Such constraints can be placed anywhere in the rule system, and the BlazeRouter HSD can automatically implement the design according to these rules. In this way, design engineers can set up and protect critical circuit topologies, ensuring that critical signals are connected in the correct order.

The tool also adds an interactive routing editor for design engineers who are comfortable with routing manually, and provides extensive special support for nets generated by constraints. This new Fast Interactive Route Editor (FIRE) features multiple Design Rule Checking (DRC) modes and new route editing capabilities. Design engineers can automatically add "Z" jacks, find differential pairs, monitor trace lengths or design according to specific constraint rules. In this way, design engineers can more easily implement dense routing designs and achieve greater routing density on fewer board layers. In addition, the tool provides a graphical feedback feature for design engineers to indicate the impact of a routing choice on other nets on the board. In the past, it was difficult for design engineers to know how changes to critical nets would affect the rest of the design. The BlazeRouter HSD graphically represents these previously elusive effects, with different colors and brightnesses representing different effects. This can help the design engineer understand the possible impact of each routing choice.

Build a complete design approach
These tools represent a major advance in addressing the high-speed issues that are prevalent in circuit board design today. However, design tools must also add more functionality to accommodate the rapidly increasing clock speeds and complexity in board design, especially as a comprehensive design approach is required to replace today's multipoint design tools. What is the design process for the new method? To address the high speed in the critical path, new functionality must be added at the design definition stage early in the process. To achieve this goal, the new method must have strong simulation and analysis capabilities. At the same time, it is essential to be able to understand key data about the board design, especially information about component availability and cost. Ideally, design engineers can achieve collaboration within the entire company through the design platform, and design engineers can not only exchange design ideas between design engineers, but also communicate with other departments such as procurement and production through the network. At the same time, the design of high-speed circuit boards relies heavily on a constraint-generating method. Currently, design engineers input electronic design data and design constraints into circuit board drawing software to implement circuit design, but the problem is further complicated by signal integrity issues and the increasing complexity of circuit board design. To address signal integrity issues on these high-speed and complex boards, they must simulate and synthesize the design before drawing the board. This places new demands on the design environment, from electrical characteristics to manufacturing processes, design engineers must formulate constraints. On an ideal design platform, design engineers can not only formulate electrical characterization rules for parameters such as trace length, EMI or crosstalk, but also set component placement rules for component spacing, height constraints, and rotation angles.

To generate such constraints quickly, the design environment must have powerful topology analysis and "what if" analysis capabilities. Allows design engineers to design and simulate network topologies in circuit diagram form, allows topology parameters to be changed in multiple simulations using a signal integrity analysis engine, and then investigates various termination schemes and aligns them with delay constraints, circuit layer options Together with trace spacing, signal integrity is minimized. This functionality should also be tightly coupled with component placement and linked to planning functionality so that design engineers can define initial component placement and understand the performance of routing strategies. All in all, the new design environment must provide powerful constraint management capabilities so that design engineers can organize and manage a multitude of information. Not only that, but this new approach to high-speed design must also provide verification capabilities later in the development process. In the past, circuit design engineers performed post-layout verification only when there were critical nets on the board, and a full comprehensive verification of the entire board design was considered complicated and time-consuming. But this view is changing because the complex interactions between thousands of nets in today's high-speed circuit board designs are difficult to predict. The way to ensure the reliability of the design is to conduct a thorough overall simulation of the entire routing PCB board design.