PCB Tech - Design of EDA accelerating vehicle gauge chip

Vehicle gauge chip belongs to a branch of semiconductor chip. At present, a big bottleneck encountered in chip design verification is the shortage of talents, which is also true for vehicle gauge chips. According to statistics, there will be about 200000 IC design practitioners in 2020, but the demand for talents by enterprises has far exceeded this number. As a result, almost every semiconductor design company is complaining that it is difficult to recruit urgently needed design verification personnel this year.

On the one hand, the shortage of chip talents lies in the deficiency of the traditional talent training mode. In this regard, we are glad to see that the country has laid out and carried out a series of EDA industry university research integration projects; On the other hand, the talent shortage is largely caused by the monopoly and closure of foreign EDA tools. This conservatism and closure makes it difficult for ordinary domestic developers to have extensive contact, let alone secondary development.

Car gauge chip is a complex software and hardware system. The on-board chip interconnection has gradually changed from the traditional simple sensor interconnection through can, mose and FlexRay bus to the complex vehicle Ethernet interconnection; The transmitted data is also upgraded from the previous debugging and diagnosis information to audio and video entertainment information and mission critical data information. With the increasing amount of data, the data content and delay certainty become more and more important, and the software in the vehicle gauge chip becomes more and more complex.

Vehicle gauge chip is also a special kind in the chip field, especially it has strict requirements for functional safety. The functional safety integrity level (ASIL) division of the vehicle gauge chip requires a series of rigorous tests and coverage reports in the design process. The traditional chip design verification methodology is difficult to effectively meet the complex requirements in the field of functional security. This challenge is also promoting the reform of design methods. The advanced design concept can greatly improve the efficiency, accelerate the design cycle and improve the chip security level.

In order to get rid of the current difficulties of vehicle specification chips, including dependence on foreign semiconductor manufacturers and EDA tools, shortage of domestic chip talents and backward design concept, we must emphasize the reform of EDA concepts, tools and methodologies.

Therefore, we put forward three suggestions for the design of acceleration vehicle gauge chip:

O1. EDA concept change

Most traditional EDA tools do not open the middle layer interface to the public, and ordinary users cannot develop again. For a long time, the product ecology has been closed and the user group has been narrow. Xinhuazhang emphasizes the use of EDA 2.0 technology and concept, and adopts the mode of chip design platform service (edaas (electronic design as a service)): tools are organically embedded in cloud native services, provide all-round open interfaces, and widely adapt to the processes of design verification. The tool interface is open and the tool itself is platform, which can make the chip design and verification more automatic and intelligent; At the same time, EDA 2.0 can also enable more people to participate in chip design through edaas and complete the work quickly and efficiently; Relying on EDA 2.0 technology is one of the most effective ways to solve the chip talent bottleneck. We hope to see more embedded engineers, system engineers and even software engineers can use EDA 2.0 technology to participate in chip design and R & D efficiently in the future.

O2, EDA tool change

EDA tools provide data support for functional safety, especially the quantitative analysis required for iso26262 certification: failure mode effect and diagnostic analysis (fmeda). When designing the vehicle gauge chip, the common means of fmeda is intentional fault injection on the chip, and then analyze the function failure probability (failure efficiency) caused by error injection, so as to evaluate the safety integrity level of the vehicle gauge chip.

Therefore, EDA tools need test incentives that can generate various fault models. Due to the large number and variety of errors to be injected into the chip, the traditional simulation tools often have low performance, consume huge memory and lengthy simulation time. This is because the traditional simulation tool engine focuses on function verification, which has huge memory and CPU overhead for fault injection.

Therefore, fault injection requires EDA company to design a special simulator engine to improve the efficiency of fault injection simulation; In addition, the chip fault injection test needs the simulator to handle more faults and execute concurrently as much as possible. Due to the regularity and symmetry of some logic in the chip, some rules can be found through formal methods, so as to reduce the number of unnecessary injections on a large scale. Once the number of test cases is reduced, the total time required for simulation can be reduced, which can also improve the efficiency of the simulator on the other hand.

Emulator is just a typical example of EDA tool change. Other tools, such as formal verification, can also make many enhancements and optimizations for functional safety, including automatic detection of safety paths and applicable error models on critical paths: including fixed open fault, transient fault, transition fault, bridge fault, etc. These technologies will greatly improve the verification efficiency of vehicle gauge chip.

O3. Design methodology reform

The difference between car gauge chip and consumer electronics chip lies in the special requirements of safety and reliability. At the beginning of the design, the vehicle gauge chip needs to do a very careful architecture exploration. The purpose of these preliminary work is to first ensure the safety, and then meet the requirements of iso26262 certification. In order to ensure the safety of design in harsh environment, the vehicle gauge chip often uses some special logic functions: for example, hardware CRC verification in data flow, single bit parity verification in on-chip SRAM and flash memory, data reading ECC verification, and chip power supply voltage detection; In the control intensive logic, redundant logic is adopted, such as multiple CPUs processing a single task at the same time, output result comparison, double watchdog system, clock circuit backup mechanism, etc. To design the logic unit related to these safety measures, it is necessary to verify its necessity, reliability and integrity at the early stage of design.

Based on practical experience, we recommend introducing the virtual model of chip function as soon as possible at the beginning of design. This development based on virtual model can enable designers and architects to analyze and optimize the system as soon as possible and explore the advantages of different architectures in security performance. On the one hand, design engineers can use these models to verify, make preliminary analysis on complex design and judge the optimal power consumption performance area without SOC real environment; On the other hand, the verification engineer can use the virtual model to develop the white box test environment as soon as possible, carry out the software and hardware collaborative test of complex systems in advance, and even compile the model in the general controller and put it in the ECU system for actual field test.

Virtual model has many advantages, but its premise is that engineers need to be widely aware of its importance and actively explore and make good use of it in design verification. At the same time, EDA manufacturers should also actively cooperate with various chip IP manufacturers to develop more rich and flexible virtual models and build an ecosystem conducive to the positive development of the industry. The shift left of verification test is the trend advocated in the field of complex chip design, and on the vehicle gauge chip, we believe that the virtual model is a perfect help point for the shift left of verification test.

In the past 20 years, we are deeply aware of the changes brought by technological development to the chip industry, but at the same time, we also increasingly need stronger technological innovation to meet the needs of our growing chip industry and solve various challenges we face. We firmly believe that relying on the change of EDA tools brought by EDA 2.0 can solve the bottleneck problem of talent and technology; Improving tools can better improve the efficiency of design verification; Extensive use of virtual models will improve the quality of architecture exploration and improve the safety of vehicle specification chips. We hope to actively explore and communicate with colleagues in various industries, make common development and progress, and contribute to the development of our national chips, including vehicle regulation chips!