PCB Tech - Board-level simulation technology in PCB board design

As the complexity and density of circuit boards continue to increase, the task of testing and debugging limited test points using oscilloscopes and logic analyzers has become more and more onerous, and the efficiency has become increasingly low. Emerging EDA simulators and waveform browsers use thousands of time domains to monitor signals, and can greatly increase the scope of debugging. This article will introduce in detail the powerful functions of board-level simulation technology and its role in shortening the circuit board design and production cycle.

No matter how advanced the development tools are, large or small defects will inevitably appear during the entire development process, and they may be lurking in various stages of design, implementation and CAD. It is not terrible to have defects. It is important to find and eliminate these defects as early as possible, so as to effectively save money and time. The role of board-level simulation tools is to help PCB designers perform debugging work faster before and after the circuit board is manufactured.

Board level simulation technology

The main steps of board level simulation are as follows:

a. Develop a test plan

The first step of the simulation is to develop a complete test plan, which should fully reflect the specific requirements of the product in terms of board-level simulation. The test plan can be divided into two stages to implement, stage 1 is a single interface test; stage 2 is the overall function test of the circuit board.

‘Phase 1’ needs to clearly define the type and scope of the interface and isolate them completely, such as the isolation between the processor and the memory interface. Then make a test case to check the connection performance and timing characteristics of the interface.

‘Stage 2’ requires the circuit board to be divided into several functional blocks (a functional block can be equipped with one or more interfaces). After each interface is confirmed to be working properly in the first stage, the target can be locked on the function of a single module, that is, the entire circuit board is regarded as a black box. At this time, you can use the detailed functions of the appropriate test vector test module to deal with the synthesized timing problems and the specific data of the function block.

b. Establishment of simulation environment

Before simulation, a complete simulation environment needs to be established to support, process and feedback various input signals and measure output signals.

The simulation environment should include the following: 1. Checker and monitor; 2. Netlist; 3. Model; 4. Directory structure;

1. Checkers and monitors

After the test plan is prepared, errors or defects are automatically recorded. When the input excitation signal is added to the circuit board, people all hope to get the ideal output result, but the simulation result may be good or bad. At this time, it takes a lot of time to analyze the output result. If you write down a script for comparison, you can avoid this time-consuming analysis work. In addition, using flags to indicate fault conditions during simulation can also achieve the same effect.

When simulating timing and data integrity issues, we call the task used to indicate defects a monitor, and the script used to simulate functional characteristics and compare the final results is called a checker. This method may take a little time at the beginning, but it can greatly reduce the time for waveform search and result analysis in the actual test phase.

2. Netlist

Commonly used schematic input tools all have the function of generating Verilog/VHDL netlists. These netlists contain all the components and the network connections between the components. In addition, the components and port names in the netlist are represented by symbols.

3. Model

The simulation requires the HDL model of each component. The Verilog/VHDL model library of the standard chip can be obtained from Synopsys or other suppliers. The functions of these models are completely similar to the actual components, and the timing can be flexibly changed to meet the latest component requirements. As mentioned above, the component and port names in the netlist are the same as the names declared when the schematic is entered, but the component and port names used in the actual model may be different from those used in the netlist. In order to connect the ports in the netlist to the model correctly, a package file needs to be created. The file only provides the port mapping relationship between the netlist and the actual model, and it is specifically designed for those components with different port names in the model and the netlist. Built. For example, the symbol name of a component pin is OE_, but the port in the model is named oe_n. At this time, such a package file is needed to establish the connection relationship between the symbol pin in the netlist and the model port.

4. Directory structure

Usually PCB designers need to establish the correct directory structure to track the input/output signals of the simulation process. These directories can be used to distinguish different types of environment files. These file types include: cs, local development models, monitors/inspectors, scripts, board-level netlists, log files, dump files, and so on. A good directory structure can facilitate management and tracking of all environment/code files.

Use the framer/deframer as the simulated functional block object (assuming that the PCI bus controller, system controller and arbiter can work normally, the test to be done is only for the framer/deframer of the system ), input the excitation signal from the PCI side, check the output result on the T1/E1 digital line side, and then do it the other way around.

The following are several typical test situations: 1. Frame with different data content; 2. Delay of frame; 3. Super frame or extended super frame with different parameter settings; 4. Frame with CRC error Wait.

You can simulate other function blocks in the same way and check the simulation results. The following defects may occur during this test phase: 1. Two different interfaces in different function blocks have the same network name, and this usually causes a short circuit. 2. System integration problems, such as signal routing jumped from one interface to another. 3. The data format of an interface cannot be supported by other interfaces. This stage is also called the data channel simulation of the circuit board.

Simulation skills

The following are some tips for board-level simulation: 1. For programmable PCB components, try to make use of back-labeling files. These files contain predictable input and output signal timing information; 2. Check all power supply network descriptions in the netlist, and fill in immediately if there are any omissions; 3. The final netlist will not be glued to the circuit board. The above components need to be noted.

Although functional simulation has some of the above outstanding advantages, it also has certain limitations, making the simulation results unable to be completely analogous to the actual PCB circuit board. This limitation is shown in: 1. The lack of different power network identifications, because in HDL, although The power supply network can be declared but the specific value cannot be indicated, such as 5V or 3.3V. The current version of HDL does not yet support this feature. 2. HDL cannot simulate an analog interface. 3. This kind of simulation cannot find problems related to drive capability. 4. Performing a memory test requires a huge dump file and a long execution time.