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PCB Blog - Signal Integrity Design for Gigabit Device PCB board

PCB Blog

PCB Blog - Signal Integrity Design for Gigabit Device PCB board

Signal Integrity Design for Gigabit Device PCB board


It introduces the application of PCB board design tools to solve these problems, such as skin effect and dielectric loss, the effect of vias and connectors, differential signaling and Cabling considerations, power distribution, and EMI control, etc. The rapid development of communication and computer technology has brought high-speed PCB design into the gigabit field. The application of new high-speed devices makes such high-speed long-distance transmission on the backplane and single board possible. Signal integrity issues (SI), power integrity and electromagnetic compatibility issues are also more prominent.

PCB board

Signal integrity refers to the quality of signal transmission on the signal line. The main problems include reflection, oscillation, timing, ground bounce and crosstalk. Poor signal integrity is not caused by a single factor, but by a combination of factors in board-level design. In the PCB design of gigabit equipment, a good signal integrity design requires engineers to fully consider the components, transmission line interconnection scheme, power distribution and EMC aspects. EDA tools for high-speed PCB design have evolved from pure simulation verification to a combination of design and verification, helping designers set rules early in design to avoid errors instead of finding problems later in design. As data rates increase and designs become more complex, high-speed PCB system analysis tools become more necessary. These tools include timing analysis, signal integrity analysis, design space parameter sweep analysis, EMC design, power system stability analysis, and more. . Here we will focus on some of the issues that should be considered in signal integrity analysis in the PCB design of gigabit devices.

High Speed Devices and Device Models
Although the gigabit transmit and receive component suppliers will provide design information about the chip, there is also a process for the device supplier to understand the signal integrity of the new device, so the design guidelines given by the device supplier may not be mature, and the One is that the design constraints given by the device suppliers are usually very strict, and it will be very difficult for the design engineer to meet all the design rules. Therefore, it is necessary for signal integrity engineers to use simulation analysis tools to analyze the supplier's constraint rules and actual designs, investigate and optimize component selection, topology, matching schemes, and values of matching components, and finally develop solutions to ensure signal integrity. The PCB layout and routing rules. Therefore, the simulation analysis of gigabit signals has become very important, and the role of the device model in the signal integrity analysis work has been paid more and more attention.

Component models usually include IBIS models and Spice models. Because the board-level simulation only cares about the signal response from the output pins to the input pins through the interconnection system, and IC manufacturers do not want to leak detailed circuit information inside the device, and the simulation time of the transistor-level Spice model is usually unbearable, so the IBIS model is used in high-speed PCBs. The design field is gradually being accepted by more and more device manufacturers and signal integrity engineers.

Engineers often question the robustness of the IBIS model when it comes to simulating PCB systems for gigabit devices. When the device works in the saturation and cut-off region of the transistor, the IBIS model lacks sufficient detailed information to describe the nonlinear region of the transient response, and the results simulated by the IBIS model cannot produce the response information that the transistor-level model can. However, for ECL type devices, an IBIS model can be obtained that is very consistent with the simulation results of the transistor-level model. The reason is very simple. The ECL driver works in the linear region of the transistor, and the output waveform is closer to the ideal waveform. According to the IBIS standard, a relatively IBIS model.

As the data transmission rate increases, the differential devices developed on the basis of ECL technology have been greatly developed. The LVDS standard and CML, among others, have made gigabit signal transmission possible. As can be seen from the above discussion, the IBIS standard is still applicable to the design of gigabit systems due to the circuit structure and the corresponding differential technology application. This is also demonstrated in some published papers applying IBIS models to 2.5Gbps LVDS and CML designs. Since the IBIS model is not suitable for describing active circuits, it is not suitable for many Gbps devices that have pre-emphasis circuits for loss compensation. Therefore, in a gigabit system design, the IBIS model works effectively only if:
1. Differential devices operate in the amplification region (linear V-I curve)
2. Device does not have active pre-emphasis circuitry
3. The device has a pre-emphasis circuit but is not enabled (with a short interconnect system enabling pre-emphasis may lead to worse results)
4. The device has passive pre-emphasis circuitry, but the circuitry can be separated from the device's die. When the data rate is 10Gbps or above, the output waveform is more like a sine wave, and the Spice model is more applicable.

Loss effect
When the signal frequency increases, the attenuation on the transmission line cannot be ignored. At this time, it is necessary to consider the loss caused by the equivalent resistance of the conductor in series and the equivalent conductance of the medium in parallel, and the lossy transmission line model needs to be used for analysis.

The equivalent model of the lossy transmission line is shown in Figure 1. It can be seen from the figure that the equivalent series resistance R and the equivalent parallel conductance G are used to characterize the loss. The equivalent series resistance R is the resistance caused by the DC resistance and the skin effect. The DC resistance is the resistance of the conductor itself, which is determined by the physical structure of the conductor and the resistivity of the conductor. When the frequency increases, the skin effect starts to work. The skin effect is a phenomenon in which the signal current in the conductor is concentrated on the surface of the conductor when the high-frequency signal passes through the conductor. Inside the conductor, the signal current density along the conductor cross-section decays exponentially, and the depth at which the current density decreases to 1/e of the original is called the skin depth. The higher the frequency, the smaller the skin depth, resulting in an increase in the resistance of the conductor. Skin depth is inversely proportional to the square root of frequency.

Equivalent parallel conductance G is also called dielectric loss (Dielectric Loss). At low frequencies, the equivalent parallel conductance is related to the bulk conductivity and equivalent capacitance of the medium, while as the frequency increases, the dielectric loss angle begins to dominate. At this time, the dielectric conductivity is determined by the dielectric loss angle and the signal frequency. Generally speaking, when the frequency is less than 1GHz, the skin effect loss plays a major role, and when the frequency is above 1GHz, the dielectric loss dominates. The dielectric constant, dielectric loss angle, conductor conductivity and cut-off frequency can be set in the simulation software. The software will consider the skin effect and dielectric loss according to the structure of the transmission line during simulation. If simulating attenuation, be sure to set the corresponding cut-off frequency according to the bandwidth of the signal. The bandwidth is determined by the signal edge rate. Many 622MHz signals are not much different from 2.5GHz signal edge rates. In addition, the equivalent can also be seen in the lossy transmission line model. Resistance and conductance vary with frequency.

Effects of Vias and Connectors
The vias transmit the signal to the other side of the board. The vertical metal part between the boards is an uncontrollable impedance, and the inflection point from the horizontal direction to the vertical direction is a break point, which will produce reflections, and its appearance should be minimized. In gigabit system design simulation, to consider the effect of vias, a via model is required. The model structure of the via is in the form of a series resistance R, an inductance L and a parallel capacitor C. According to the specific application and accuracy requirements, multiple RLC structures can be used in parallel, and the coupling with other conductors can be considered. At this time, the via model is a matrix. There are two ways to obtain the via model, one is obtained by testing such as TDR, and the other can be extracted by the 3D field extractor (Field Solver) according to the physical structure of the via. Via model parameters are related to the PCB material, stackup, thickness, pad/antipad size, and how the wires that connect to it are connected. In the simulation software, different parameters can be set according to the accuracy requirements, the software will extract the model of the via hole according to the corresponding algorithm and consider its influence during simulation.

In the design of the gigabit system PCB, the influence of the connector should be considered in particular. Now the development of high-speed connector technology can well ensure the continuity of the impedance and the ground plane during signal transmission. The simulation analysis of the connector in the design is mainly A multi-line model is used. The connector multi-line model is a model extracted by considering the inductive and capacitive coupling between pins in three-dimensional space. The connector multi-line model generally uses a three-dimensional field extractor to extract the RLGC matrix, which is generally in the form of a Spice model sub-circuit. Due to the complex structure of the model, it takes a long time for extraction and simulation analysis. In SpecctraQuest software, the Spice model of the connector can be edited into an Espice model, which can be assigned to the device or called directly, or it can be edited into a package model in DML format and assigned to the device for use.

Differential Signaling and Routing Considerations
Differential signal has the advantages of strong anti-interference and high transmission rate. In gigabit signal transmission, it can better reduce the influence of crosstalk and EMI. Its coupling forms include edge coupling and up-down coupling, loose coupling and tight coupling. Compared with top and bottom coupling, edge coupling has the advantages of better reduction of crosstalk, convenient wiring, and simple processing. Top and bottom coupling is more often applied to PCB boards with high wiring density. Compared with loose coupling, tight coupling has better anti-interference ability and can reduce crosstalk, and loose coupling can better control the continuity of differential trace impedance. The specific differential routing rules should consider the effects of impedance continuity, loss, crosstalk, and trace length differences according to different situations. Differential lines use eye diagrams to analyze simulation results. The simulation software can set the random sequence code to generate the eye diagram, and can input the jitter and offset parameters to analyze its influence on the eye diagram.

Power Distribution and EMC
The increase in data transfer rates, accompanied by faster edge rates, requires power supply stability over a wider frequency band. A high-speed system may pass a transient current of 10A and require a power supply ripple of 50mV, which means that the impedance of the power distribution network must be within 5mΩ within a certain frequency range. For example, the rise time of the signal is less than 0.5ns, which should be considered. The bandwidth range is up to 1.0GHz. In the design of gigabit systems, it is necessary to avoid the interference of synchronization noise (SSN) and ensure that the power distribution system has a low impedance in the bandwidth range. Generally, in the low frequency band, decoupling capacitors are used to reduce the impedance, and in the high frequency band, the distribution of the power supply and the ground plane is mainly considered. Figure 4 shows the frequency response plot of impedance change with and without decoupling capacitors in the power and ground plane layers.

SpecctraQuest software can analyze the influence of synchronous noise caused by the package structure. The Power Integrity (PI) software uses the frequency domain to analyze the power distribution system, which can effectively analyze the number and location of decoupling capacitors, as well as the influence of power and ground planes. Engineers perform decoupling capacitor selection as well as placement, routing, and planar distribution analysis.

EMC stands for Electromagnetic Compatibility, and the resulting problems include excessive electromagnetic radiation and susceptibility to electromagnetic radiation. The main reason for it is that the circuit operating frequency is too high and the layout and wiring are unreasonable. At present, there are software tools for EMC simulation, but EMC problems can be caused by many electromagnetic reasons. It is difficult to set simulation parameters and boundary conditions, which will directly affect the accuracy and practicability of simulation results. The usual practice is to apply the design rules that control EMC to each link of the design, to achieve rule-driven and control in each link of the design, and after the design is tested and verified, new rules can be formed and applied to the new PCB board design.