PCB Tech - Signal reflow and cross-segmentation in high-speed PCB

What is the signal reflow and cross-segmentation in high-speed PCB?

IC1 is the signal output terminal, IC2 is the signal input terminal (in order to simplify the PCB model w ww.pcblx.com, assuming that the receiving terminal contains a resistor connected below) the third layer is the ground layer. The grounds of IC1 and IC2 are both from the third ground plane. The upper right corner of the top layer is a power plane, which is connected to the positive pole of the power supply. C1 and C2 are the decoupling capacitors of IC1 and IC2 respectively. The power supply and ground pin of the chip shown in the figure are the power supply and ground of the signal sending and receiving ends.

At low frequencies, if the S1 terminal outputs a high level, the entire current loop is that the power supply is connected to the VCC power plane through the wire, and then enters IC1 through the orange path, and then comes out from the S1 terminal, and enters IC2 through the R1 terminal along the second layer of wire. Then enter the GND layer and return to the negative pole of the power supply via the red path.

But at high frequencies, the distribution characteristics of the PCB board will have a great influence on the signal. The ground return we often talk about is a problem often encountered in high-frequency signals. When there is an increased current in the signal line from S1 to R1, the external magnetic field changes quickly, which will induce a reverse current in nearby conductors. If the ground plane of the third layer is a complete ground plane, there will be a blue dotted current on the ground plane; if the TOP layer has a complete power plane, there will also be a blue line on the top layer. Dotted reflux. At this time, the signal loop has the smallest current loop, the energy radiated to the outside is the smallest, and the ability to couple external signals is also the smallest. (The skin effect at high frequency is also the smallest outward radiation energy, the principle is the same.) Because the high frequency signal level and current change very quickly, but the change period is short, the required energy is not very large, so the chip is The decoupling capacitor closest to the chip is powered. When C1 is large enough and the response is fast enough (it has a very low ESR value, ceramic capacitors are usually used. The ESR of ceramic capacitors is much lower than that of tantalum capacitors.), the orange path on the top layer and the red path on the GND layer can be It is regarded as non-existent (there is a current corresponding to the power supply of the entire board, but not the current corresponding to the signal shown in the figure).

Therefore, according to the environment constructed in the figure, the entire path of the current is: from the positive pole of C1-"VCC of IC1-" S1- "L2 signal line-" R1- "GND of IC2-" via-"GND layer yellow Path-"Via -" Capacitor negative pole. It can be seen that there is a brown equivalent current in the vertical direction of the current, and a magnetic field will be induced in the middle. At the same time, this torus can easily couple to external interference. If the signal in the figure is a clock signal, there is a set of 8bit data lines in parallel, powered by the same power supply of the same chip, and the current return path is the same. If the data line level flips in the same direction at the same time, a large reverse current will be induced on the clock. If the clock line is not well matched, this crosstalk is enough to have a fatal effect on the clock signal. The intensity of this kind of crosstalk is not proportional to the absolute value of the interference source's high and low levels, but proportional to the current change rate of the interference source. For a purely resistive load, the crosstalk current is proportional to dI/dt=dV /(T10%-90%*R). In the formula, dI/dt (rate of change of current), dV (swing amplitude of interference source) and R (interference source load) all refer to the parameters of the interference source (if it is a capacitive load, dI/dt is the same as T10%- The square of 90% is inversely proportional.). It can be seen from the formula that the crosstalk of low-speed signals is not necessarily smaller than that of high-speed signals. That is what we said: 1kHZ signal is not necessarily a low-speed signal, we must comprehensively consider the situation of the edge. For a signal with a steep edge, it contains a lot of harmonic components, and has a large amplitude at each frequency multiplication point. Therefore, you should also pay attention when selecting devices. Don't blindly choose chips with fast switching speeds. Not only will the cost be high, but it will also increase crosstalk and EMC problems.

Any adjacent power plane or other plane, as long as there is a suitable capacitor at both ends of the signal to provide a low-reactive path to GND, then this plane can be used as a return plane for this signal. In normal applications, the corresponding chip IO power supply is often the same for receiving and sending, and there are generally 0.01-0.1uF decoupling capacitors between each power supply and ground, and these capacitors are also at the two ends of the signal, so the The reflow effect of the power plane is second only to the ground plane. However, if other power planes are used for return flow, there is often no low reactance path to the ground at both ends of the signal. In this way, the current induced in the adjacent plane will find the nearest capacitance and return to ground. If the "nearest capacitor" is far away from the start or end, the return will have to travel a long distance to form a complete return path, and this path is also a return path for adjacent signals, and this same return flow The effect of road and common ground interference is the same, which is equivalent to crosstalk between signals.

For some unavoidable cross-supply splitting situations, you can connect a capacitor or a high-pass filter (such as a 10 ohm resistor string 680p capacitor) formed by a capacitor or RC series across the split. The specific value depends on your own signal type, namely To provide a high-frequency PCB return path, but also to isolate the low-frequency crosstalk between the mutual planes). This may involve the problem of adding capacitors between the power planes, which seems a bit funny, but it is definitely effective. If some specifications do not allow it, the two planes of the division can be separately led to the ground.

In the case of borrowing other planes for return flow, it is best to add a few small capacitors to the ground at both ends of the signal to provide a return path. But this approach is often difficult to achieve. Because most of the surface space near the terminal is occupied by the matching resistor and the decoupling capacitor of the chip.