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Electronic Design

Electronic Design

Electronic Design

Electronic Design

How to solve EMI in multi-layer PCB design
2021-09-20
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Author:Aure

How to solve EMI in multi-layer PCB design

Circuit board manufacturers: reasonably place capacitors of moderate capacity around the IC's power supply pins, which can make the jump of the IC's output working voltage come quickly.As everyone knows, the problem is not unforgivable. Because the capacitor has a limited frequency response performance, this makes it impossible for the capacitor to be converted into the harmonic power required to cleanly drive the IC output in the full frequency band.

In addition, the transient voltage formed on the power bus will cause a voltage drop on both sides of the inductance of the decoupling path, and these transient voltages are also the main source of common mode EMI interference. How should we deal with these problems?

As far as the IC on our circuit board is concerned, the power layer around the IC can also be regarded as an excellent high-frequency capacitor, and it can also collect the part of the energy leaked by the discrete capacitor that guarantees a clean output of high-frequency energy.

In addition, the inductance of a good power layer should be small, and the transient signal synthesized by the inductance is also small, so as to reduce the common mode EMI.

Of course, the connection line from the power layer to the IC power pin must be as short as possible, because the rising edge of the digital signal becomes faster, and it is best to connect it directly to the pad where the IC power pin is located. This needs to be discussed separately.

In order to control common-mode EMI, the power plane should help decoupling and have a sufficiently low inductance. This power plane must be a pair of well-designed power planes. Someone may ask, how good is good?



How to solve EMI in multi-layer PCB design


The answer to the question depends on the layering of the switching power supply, the material between the layers, and the operating frequency (that is, a function of the IC rise time).

Generally, the spacing of the power layer is 6mil, and the interlayer is FR4 material, the equivalent capacitance of the power layer per square inch is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.

There are not many components with a rise time of 100 to 300 ps, but according to the current IC development speed, components with a rise time in the range of 100 to 300 ps will occupy a high proportion.

For circuit boards with a rise time of 100 to 300 ps, 3mil layer spacing will no longer be suitable for most applications. At that time, layering technology with a layer spacing of less than 1 mil had to be used, and materials with a high dielectric constant were used to replace FR4 dielectric materials.

Now, ceramics and ceramic plastics can meet the design requirements of 100 to 300ps rise time control circuits.

Although new materials and new methods may be used in the future, for today's common 1 to 3ns rise time circuits, 3 to 6mil layer spacing and FR4 dielectric materials, it is generally sufficient to solve high-end harmonics and make transient data signals sufficiently low , I think, common mode EMI can be reduced very low. The PCB circuit board hierarchical stacking design case given in this article will assume that the layer spacing is 3 to 6 mils.

Electromagnetic shielding From the perspective of signal routing, a good layering strategy should be to put all signal wiring on one or several layers, and these layers are next to the power layer or ground layer.

For power, a good surface layer strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we are talking about as a "layered" strategy.

PCB stacking Which stacking strategy is beneficial to shielding and suppressing EMI? The following block stacking scheme assumes that the power supply current flows on a single layer, and single voltage or multiple voltages are spread over different parts of the same layer. The case of multiple power layers will be discussed later.

4-Layer Board 4-Layer Board design has several potential problems. First of all, the traditional four-layer board with a thickness of 62 mils, even if the signal layer is on the surface, and the power and ground layers are on the inner layer, the distance between the power layer and the ground layer is still too large.

If the cost requirement is first, you can also consider the following two alternatives to the traditional 4-layer board. These two schemes can improve the performance of EMI control, but they are only suitable for situations where the density of on-board components is low enough and there is enough area around the components (place the required power copper layer).

The first is the preferred option. The surface layer of the pcb circuit board is the ground layer, and the middle double layer is the signal/power layer.

The power supply on the signal layer is wired with a wide line, which can make the path characteristic impedance of the power supply current low, and the impedance of the signal microstrip relative to the path is also low.

From the perspective of EMI control, it is also the best existing 4-layer pcb circuit board structure. In the second scheme, power and ground are used in the inner layer, and signals are used in the middle layer. Compared with the traditional 4-layer board, this plan has a smaller improvement, and the interlayer impedance is the same as the traditional 4-layer board.

If you want to control the wiring impedance, the above-mentioned stacking scheme should also be very careful to place the wiring under the copper island for power and grounding. On the other hand, the power supply or the copper islands on the ground layer should be interconnected as far as possible to ensure DC and low-frequency connectivity.